AD9689-2000EBZ datasheet(53/134 Pages) AD

53 / 134 page

Data Sheet

AD9689

Rev. A | Page 53 of 134

Setting Up the Multichannel NCO Feature

The first step to configure the multichannel NCO is to program

the FTWs. The AD9689 memory map has an FTW index

channel receives the FTW from the register map. The following

sequence describes the method for programming the FTWs:

1. Write the FTW index register with the desired DDC channel.

2. Write the FTW with the desired value. This value is applied

to the NCO channel index mentioned in Step 1.

3. Repeat Step 1 and Step 2 for other NCO channels.

After setting the FTWs, the user must then select an active

NCO channel. This selection can be performed either through

the SPI registers or through the external GPIO pins. The following

sequence describes the method for selecting the active NCO

channel using the SPI:

1. Set the NCO channel select mode bits (Bits[7:4] in

2. Choose the active NCO channel using Bits[3:0] in

and Register 0x0374.

The following sequence describes the method for selecting the

active NCO channel using the GPIO CMOS pins:

1. Set the NCO channel select mode bits (Bits[7:4] in

selection.

2. Configure the GPIO pins as NCO channel selection inputs

by writing to Register 0x0040, Register 0x0041, and

3. NCO switching is performed by externally controlling the

GPIO CMOS pins.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW).

The initial reset value of each PAW is set to zero and incremented

every clock cycle. The instantaneous phase of the NCO is

calculated using the PAW, FTW, MAW, MBW, and POW. Due to

this architecture, the FTW and POW registers can be updated at

any time while still maintaining deterministic phase results in

the PAW of the NCO.

Two methods can be used to synchronize multiple PAWs within

the chip:

•

Using the SPI. Use the DDC soft reset bit in the DDC

synchronization control register (Register 0x0300, Bit 4) to

reset all the PAWs in the chip. This reset is accomplished

by setting the DDC soft reset bit high, and then setting this

bit low. Note that this method can only be used to

synchronize DDC channels within the same chip.

•

Using the SYSREF± pin. When the SYSREF± pin is enabled

in the SYSREF control registers (Register 0x0120 and

in the DDC synchronization control register (Register 0x0300,

Bits[1:0]), any subsequent SYSREF± event resets all the

PAWs in the chip. Note that this method can be used to

synchronize DDC channels within the same chip or DDC

channels within separate chips.

NCO Multichip Synchronization

In some applications, it is necessary to synchronize all the

NCOs and local multiframe clocks (LMFCs) within multiple

devices in a system. For applications requiring multiple NCO

tuning frequencies in the system, a designer is likely to need to

generate a single SYSREF pulse at all devices simultaneously. For

many systems, generating or receiving a single-shot SYSREF

pulse at all devices is challenging because of the following

factors:

•

Enabling or disabling the SYSREF pulse is often an

asynchronous event.

•

Not all clock generation chips support this feature.

For these reasons, the AD9689 contains a synchronization

triggering mechanism that allows the following:

•

Multichip synchronization of all NCOs and LMFCs at

system startup.

•

Multichip synchronization of all NCOs after applying new

tuning frequencies during normal operation.

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