AD9689-2000EBZ datasheet(82/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 82 of 134

Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs)

40 ×

fOUT MbPS

fOUT = fS/10 (MHz)

fS (MHz)

F = 4

14-BIT

ADC CORE

DDC 1

(REAL INPUT,

DCM = 10

C2R = BYPASS)

M3(Q)

M2(I)

VIN_B

REAL

14-BIT

ADC CORE

DDC 0

(REAL INPUT,

DCM = 10

C2R = BYPASS)

JESD204B LINK

(L = 2 M = 4 F = 4,

S = 1, N’ = 16, N = 16,

CS = 0, HD = 0)

M1(Q)

M0(I)

LAB0

LAB1

SYNC~

VIN_A

REAL

I = REAL COMPONENT

Q = QUADRATURE COMPONENT

DCM = DECIMATION

C2R = COMPLEX TO REAL

MX = VIRTUAL CONVERTER X

LY = LANE Y

SZ = SAMPLE Z INSIDE A JESD204B FRAME

C = CONTROL BIT (OVER RANGE, AMONG OTHERS)

T = TAIL BIT

Figure 142. Two ADCs Plus Two DDCs Mode (L = 2, M = 4, F = 4, S = 1)

This example shows the flexibility in the digital and lane

configurations for the AD9689. The sample rate is 2.4576 GSPS,

whereas the outputs are all combined in a combination of either

two, four, or eight lanes, depending on the input/output speed

capability of the receiving device.

The AD9689 is set up as shown in Figure 142, with the following

configuration:

•

Two 14-bit converters at 2.4576 GSPS.

•

Two DDC application layer mode with complex outputs (I/Q).

•

Chip decimation ratio = 10.

•

DDC decimation ratio = 10 (see Table 33).

The JESD204B output configuration is as follows:

•

Four virtual converters required (see Table 33).

•

Output sample rate (fOUT) = 2457.6/10 = 245.76 MSPS.

The JESD204B supported output configurations are as follows

(see Table 33):

•

N΄ = 16 bits.

•

N = 14 bits.

•

L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2.

•

CS = 0.

•

K = 32.

•

Output serial lane rate = 9.8304 Gbps per lane (L = 2),

4.9152 Gbps per lane (L = 4), or 2.4576 Gbps per lane (L = 8).

For L = 2, set the PLL control register, Register 0x056E, to 0x00.

For L = 4, set the PLL control register, Register 0x056E, to 0x10.

For L = 8, set the PLL control register, Register 0x056E, to 0x50.

Set up the AD9689 in this mode using the following sequence:

1. Write 0x81 to Register 0x0000 (SPI soft reset).

2. Wait 5 ms to 10 ms.

3. Write 0x02 to Register 0x0200 (two DDC mode).

4. Write 0x06 to Register 0x0201 (chip decimation ratio = 10).

5. Write 0x47 to Register 0x0310 (6 dB gain, decimation ratio

set by Register 0x0311, Bits[7:4]).

6. Write 0x20 to Register 0x0311 (decimate by 10, DDC0

inputs from Channel A).

7. Register 0x0316 to Register 0x031B is the DDC0 NCO

tuning word.

8. Write 0x47 to Register 0x0330 (6 dB gain, decimation ratio

set by Register 0x0331, Bits[7:4]).

9. Write 0x25 to Register 0x0331 (decimate by 10, DDC1

inputs from Channel B).

10. Register 0x0336 to Register 0x033B is the DDC0 NCO

tuning word.

11. Write 0x15 to Register 0x0571 (JESD204B link power down).

12. Write 0x81 to Register 0x058B (scrambling enabled, L = 2).

13. Write 0x03 to Register 0x058E (M = 4).

14. Write 0x03 to Register 0x058C (F = 4).

15. Write 0x00 to Register 0x056E (lane rate = 6.75 Gbps to

13.5 Gbps).

16. Write 0x14 to Register 0x0571 (JESD204B link power up).

17. Wait 5 ms to 10 ms.

18. Read Register 0x056F (PLL status register).

19. Write 0x4F to Register 0x1228.

20. Write 0x0F to Register 0x1228.

21. Write 0x00 to Register 0x1222.

22. Write 0x04 to Register 0x1222.

23. Write 0x00 to Register 0x1222.

24. Write 0x08 to Register 0x1262.

25. Write 0x00 to Register 0x1262.

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