AD9689-2000EBZ datasheet(1/134 Pages) AD

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14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B,

Dual Analog-to-Digital Converter

Data Sheet

AD9689

Rev. A

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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

FEATURES

JESD204B (Subclass 1) coded serial digital outputs

Support for lane rates up to 16 Gbps per lane

Noise density

−152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p

−154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p

−154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p

−155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p

1.55 W total power per channel at 2.56 GSPS (default settings)

SFDR at 2.56 GSPS encode

73 dBFS at 1.8 GHz AIN at −2.0 dBFS

59 dBFS at 5.53 GHz AIN at −2.0 dBFS

full-scale voltage = 1.1 V p-p

SNR at 2.56 GSPS encode

59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS

53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS

full-scale voltage = 1.1 V p-p

SFDR at 2.0 GSPS encode

78 dBFS at 900 MHz AIN at −2.0 dBFS

62 dBFS at 5.53 GHz AIN at −2.0 dBFS

full-scale voltage = 1.1 V p-p

SNR at 2.0 GSPS encode

62.7 dBFS at 900 MHz AIN at −2.0 dBFS

53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS

full-scale voltage = 1.1 V p-p

0.975 V, 1.9 V, and 2.5 V dc supply operation

9 GHz analog input full power bandwidth (−3 dB)

Amplitude detect bits for efficient AGC implementation

Programmable FIR filters for analog channel loss equalization

2 integrated, wideband digital processors per channel

48-bit NCO

Programmable decimation rates

Phase coherent NCO switching

Up to 4 channels available

Serial port control

Supports 100 MHz SPI writes and 50 MHz SPI reads

Integer clock with divide by 2 and divide by 4 options

Flexible JESD204B lane configurations

On-chip dither

APPLICATIONS

Diversity multiband and multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A

Electronic test and measurement systems

Phased array radar and electronic warfare

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

FUNCTIONAL BLOCK DIAGRAM

ADC

CORE

FAST

DETECT

SIGNAL

MONITOR

DIGITAL DOWN-

CONVERTER

DIGITAL DOWN-

CONVERTER

14

BUFFER

VIN+A

VIN–A

VIN+B

CLK+

CLK–

VREF

PDWN/STBY

SYSREF±

AGND

DRGND

DGND

AVDD1

(0.975V)

DVDD

(0.975V)

DRVDD1

(0.975V)

DRVDD2

(1.9V)

SPIVDD

(1.9V)

AVDD2

(1.9V)

AVDD3

(2.5V)

AVDD1_SR

(0.975V)

SPI AND

CONTROL

REGISTERS

SDIO SCLK

CSB

VIN–B

BUFFER

ADC

CORE

÷2

÷4

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERDOUT4±

SERDOUT5±

SERDOUT6±

SERDOUT7±

JESD204B

LINK

AND

Tx

OUTPUTS

8

JESD204B

SUBCLASS 1

CONTROL

CLOCK

DISTRIBUTION

SYNCINB±

GPIO_A1

FD_A/GPIO_A0

FD_B/GPIO_B0

GPIO_B1

GPIO MUX

AD9689

Figure 1.

Số phần tương tự - AD9689-2000EBZ

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Analog Devices	AD9680	3Mb / 97P	Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter REV. C
	AD9680	3Mb / 99P	Dual Analog-to-Digital Converter Rev. C
	AD9680-1000EBZ	3Mb / 97P	Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter REV. C
	AD9680-1000EBZ	3Mb / 99P	Dual Analog-to-Digital Converter Rev. C
	AD9680-1250EBZ	3Mb / 97P	Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter REV. C

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