AD9689-2000EBZ datasheet(33/134 Pages) AD

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Giải thích chi tiết về linh kiện	Dual Analog-to-Digital Converter

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33 / 134 page

Data Sheet

AD9689

Rev. A | Page 33 of 134

Figure 88 shows a preferred method for clocking the AD9689.

The low jitter clock source is converted from a single-ended

signal to a differential signal using an RF transformer.

1:2Z

CLOCK INPUT

ADC

CLK+

CLK–

Figure 88. Transformer-Coupled Differential Clock

Another option is to ac couple a differential LVPECL or CML

signal to the sample clock input pins, as shown in Figure 89 and

Figure 90, respectively.

ADC

CLOCK

INPUT

CLK+

CLK–

150Ω

LVDS

DRIVER

100Ω

DIFFERENTIAL

TRACE

Figure 89. Differential LVPECL Sample Clock

ADC

CLOCK

INPUT

CLK+

CLK–

CML

DRIVER

DIFFERENTIAL

TRACE

Figure 90. Differential CML Sample Clock

In some instances, the RF DAC series such as the AD9172 has a

synthesizer that can output a clock output to clock the AD9689.

Figure 91 shows the arrangement where the AD9172 clock

outputs clock the AD9689.

ADC

CLOCK

INPUT

CLK+

CLK–

DAC

CLOCK

INPUT

CLKOUT+

CLKOUT–

AD9172

Figure 91. DAC Clock Output Clocking the AD9689

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