AD9689-2000EBZ datasheet(74/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 74 of 134

SERDOUTx+

DRVDD

SERDOUTx–

OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL

ADJUSTABLE TO

1 × DRVDD1, 0.75 × DRVDD1

100Ω

0.1µF

RECEIVER

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 135. AC-Coupled Digital Output Termination Example

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9689 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 0.85 × DRVDD1 V p-p swing at the

receiver (see Figure 135). The swing is adjustable through the

SPI registers. AC coupling is recommended to connect to the

receiver. See the Memory Map section (Register 0x05C0 to

The AD9689 digital outputs can interface with custom

application specific integrated circuits (ASICs) and field

programmable gate array (FPGA) receivers, providing superior

switching performance in noisy environments. Single point to

point network topologies are recommended with a single

differential 100 Ω termination resistor placed as close to the

receiver inputs as possible.

If there is no far end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and at equal lengths.

Figure 136 to Figure 138 show an example of the digital output

data eye, jitter histogram, and bathtub curve for one AD9689

lane running at 16 Gbps. The format of the output data is twos

complement by default. To change the output data format, see

the Memory Map section (Register 0x0561 in Table 51).

Figure 136. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps

Figure 137. Digital Outputs Jitter Histogram, External 100 Ω Terminations at

16 Gbps

Figure 138. Digital Outputs Bathtub Curve, External 100 Ω Terminations at

16 Gbps

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link can cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it can increase electromagnetic interference (EMI). See

the Memory Map section (Register 0x05C4 to Register 0x05CB

in Table 51) for more details.

Phase-Locked Loop (PLL)

The PLL generates the serializer clock, which operates at the

JESD204B lane rate. The status of the PLL lock can be checked

in the PLL locked status bit (Register 0x056F, Bit 7). This read

only bit notifies the user if the PLL achieved a lock for the

specific setup. Register 0x056F also has a loss of lock (LOL)

sticky bit (Bit 3) that notifies the user that a LOL is detected. The

sticky bit can be reset by issuing a JESD204B link restart

(Register 0x0571 = 0x15, followed by Register 0x0571 = 0x14).

Refer to Table 32 for the reinitialization of the link following a

link power cycle.

The JESD204B lane rate control, Bits[7:4] of Register 0x056E,

must be set to correspond with the lane rate. Table 31 shows the

lane rates supported by the AD9689 using Register 0x056E.

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