AD9689-2000EBZ datasheet(93/134 Pages) AD

93 / 134 page

Data Sheet

AD9689

Rev. A | Page 93 of 134

TEST MODES

ADC TEST MODES

The AD9689 has various test options that aid in the system level

implementation. The AD9689 has ADC test modes that are

available in Register 0x0550. These test modes are described in

Table 39. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks,

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The pseudorandom number (PN) generators

from the PN sequence tests can be reset by setting Bit 4 or Bit 5

of Register 0x0550. These tests can be performed with or

without an analog signal (if present, the analog signal is

ignored); however, they do require an encode clock.

If the application mode is set to select a DDC mode of

operation, the test modes must be enabled for each DDC

enabled. The test patterns can be enabled via Bit 2 and Bit 0 of

depending on which DDC(s) are selected. The (I) data uses the

test patterns selected for Channel A, and the (Q) data uses the

test patterns selected for Channel B. For DDC3 only, the (I) data

uses the test patterns from Channel A, and the (Q) data does

not output test patterns. Bit 0 of Register 0x0387 selects the

Channel A test patterns to be used for the (I) data. For more

information, see the AN-877 Application Note.

ADC TEST PATTERNS

(0x0550,

0x0551 TO 0x0558)

JESD204B LONG

TRANSPORT TEST

PATTERN

0x0571[5]

JESD204B

INTERFACE TEST

PATTERN

(0x0573,

0x0551 TO 0x0558)

JESD204B DATA

LINK LAYER TEST

PATTERNS

0x0574[2:0]

JESD204B SAMPLE

CONSTRUCTION

TAIL BITS

0x0571[6]

A13

MSB

LSB

A12

A11

A10

A13

A12

A11

A10

MSB

LSB

CONTROL BITS

ADC

SERDOUT0±

SERDOUT3±

SERDOUT2±

SERDOUT1±

FRAME

CONSTRUCTION

SERIALIZER

SYMBOL0 SYMBOL1

SCRAMBLER

1 + x14 + x15

(OPTIONAL)

a b

i j a b

i j

a b c d e f g h i j

MSB

LSB

8-BIT/

10-BIT

ENCODER

Figure 156. ADC Output Datapath Showing Test Pattern Injection Points

Table 39. ADC Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default/

Seed Value

Sample (N, N + 1, N + 2, …)

0000

Off (default)

Not applicable

0001

Midscale short

0000 0000 0000

Not applicable

0010

Positive full-scale short

01 1111 1111 1111

Not applicable

0011

Negative full-scale short

10 0000 0000 0000

Not applicable

0100

Checkerboard

10 1010 1010 1010

Not applicable

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0101

PN sequence long

x23 + x18 + 1

0x3AFF

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0110

PN sequence short

x9 + x5 + 1

0x0092

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0111

One-/zero-word toggle

11 1111 1111 1111

Not applicable

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

1000

User input

Not applicable

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

User Pattern 1[15:2] … for repeat mode

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

0x0000 … for single mode

1111

Ramp output

(x) % 214

Not applicable

(x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214

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