AD9689-2000EBZ datasheet(96/134 Pages) AD

96 / 134 page

AD9689

Data Sheet

Rev. A | Page 96 of 134

SERIAL PORT INTERFACE

The AD9689 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields. These fields are documented

in the Memory Map section. For detailed operational information,

see the Serial Control Interface Standard (Rev. 1.0).

CONFIGURATION USING THE SPI

Three pins define the SPI of the AD9689 ADC: the SCLK pin,

the SDIO pin, and the CSB pin (see Table 44). The SCLK (serial

clock) pin synchronizes the read and write data presented

from/to the ADC. The SDIO (serial data input/output) pin is a

dual-purpose pin that allows data to be sent and read from the

internal ADC memory map registers. The CSB (chip select bar)

pin is an active low control that enables or disables the read and

write cycles.

Table 44. SPI Pins

Function

SCLK

Serial clock. The serial shift clock input that is used to

synchronize serial interface, reads, and writes.

SDIO

Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 4 and

Table 5.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB can stall high between

bytes to allow additional external timing. When CSB is tied

high, SPI functions are placed in a high impedance mode. This

mode turns on any SPI pin secondary functions.

All data is composed of 8-bit words. The first bit of each

individual byte of serial data indicates whether a read or write

command is issued, which allows the SDIO pin to change

direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a

readback operation, performing a readback causes the SDIO pin

to change direction from an input to an output at the appropriate

point in the serial frame.

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the Serial Control Interface Standard

(Rev. 1.0).

HARDWARE INTERFACE

The pins described in Table 44 comprise the physical interface

between the user programming device and the serial port of the

AD9689. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note.

Do not activate the SPI port during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is

used for other devices, it may be necessary to provide buffers

between this bus and the AD9689 to prevent these signals from

transitioning at the converter inputs during critical sampling

periods.

SPI ACCESSIBLE FEATURES

Table 45 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the Serial Control Interface Standard (Rev. 1.0). The AD9689

device specific features are described in the Memory Map section.

Table 45. Features Accessible Using the SPI

Feature

Description

Mode

Allows the user to set either power-down mode or standby mode.

Clock

Allows the user to access the clock divider via the SPI.

DDC

Allows the user to set up decimation filters for different applications.

Test Input/Output

Allows the user to set test modes to have known data on output bits.

Output Mode

Allows the user to set up outputs.

Serializer/Deserializer (SERDES) Output Setup

Allows the user to vary SERDES settings such as swing and emphasis.

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