AD9689-2000EBZ datasheet(73/134 Pages) AD

73 / 134 page

Data Sheet

AD9689

Rev. A | Page 73 of 134

The SYNCINB± pin operation can also be controlled by the

SPI. The SYNCINB± signal is a differential dc-coupled LVDS

mode signal by default, but it can also be driven single-ended.

For more information on configuring the SYNCINB± pin

operation, refer to Register 0x0572.

The SYNCINB± pins can also be configured to run in CMOS

(single-ended) mode, by setting Bit 4 in Register 0x0572. When

running SYNCINB± in CMOS mode, connect the CMOS

SYNCINB signal to Pin N13 (SYNCINB+) and leave Pin P13

(SYNCINB−) floating.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with

an /R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe, the link configuration data is sent, starting

with the third character. The second character is a /Q/ character

to confirm that the link configuration data is to follow. All

undefined data slots are filled with ramp data. The ILAS

sequence is never scrambled.

The ILAS sequence construction is shown in Figure 134. The

four multiframes include the following:

•

Multiframe 1 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 2 begins with an /R/ character followed by a

/Q/ character (/K28.4/), followed by link configuration

parameters over 14 configuration octets (see Table 30) and

ends with an /A/ character. Many of the parameter values

are of the value − 1 notation.

•

Multiframe 3 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 4 begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

User Data and Error Detection

After the initial lane alignment sequence completes, the user

data is sent. Normally, within a frame, all characters are considered

to be user data. However, to monitor the frame clock and

multiframe clock synchronization, there is a mechanism for

replacing characters with /F/ or /A/ alignment characters when

the data meets certain conditions. These conditions are

different for unscrambled and scrambled data. The scrambling

operation is enabled by default; however, it can be disabled

using the SPI.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a

multiframe is replaced by an /A/. The JESD204B receiver (Rx)

checks for /F/ and /A/ characters in the received data stream

and verifies that they only occur in the expected locations. If an

unexpected /F/ or /A/ character is found, the receiver handles

the situation by using dynamic realignment or asserting the

SYNCINB± signal for more than four frames to initiate a

resynchronization. For unscrambled data, if the final character

of two subsequent frames is equal, the second character is

replaced with an /F/ if it is at the end of a frame, and an /A/ if

it is at the end of a multiframe.

Insertion of alignment characters can be modified using the

SPI. The frame alignment character insertion (FACI) is enabled

by default. More information on the link controls is available in

the Memory Map section, Register 0x0571.

8-Bit/10-Bit Encoder

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed.

The control characters used in JESD204B are shown in Table 30.

The 8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

The 8-bit/10-bit interface has options that can be controlled via

the SPI. These operations include bypass and invert, and are

troubleshooting tools for the verification of the digital front end

(DFE). See the Memory Map section, Register 0x0572, Bits[2:1]

for information on configuring the 8-bit/10-bit encoder.

START OF

ILAS

●●●

END OF

MULTIFRAME

START OF LINK

CONFIGURATION DATA

START OF

USER DATA

●●●

Figure 134. Initial Lane Alignment Sequence

Table 30. AD9689 Control Characters Used in JESD204B

Abbreviation

Control Symbol

8-Bit Value

10-Bit Value, RD = −1

10-Bit Value, RD = +1

Description

/R/

/K28.0/

000 11100

001111 0100

110000 1011

Start of multiframe

/A/

/K28.3/

011 11100

001111 0011

110000 1100

Lane alignment

/Q/

/K28.4/

100 11100

001111 0100

110000 1101

Start of link configuration data

/K/

/K28.5/

101 11100

001111 1010

110000 0101

Group synchronization

/F/

/K28.7/

111 11100

001111 1000

110000 0111

Frame alignment

RD means running disparity.

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