AD9689-2000EBZ datasheet(108/134 Pages) AD

108 / 134 page

AD9689

Data Sheet

Rev. A | Page 108 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0315 DDC0 phase

control

[7:4] Reserved

Reserved.

0x0

[3:0] DDC0 phase update

index

Indexes the NCO channel whose phase and offset is updated. The

update method is based on the DDC phase update mode, which

can be continuous or require chip transfer.

0x0

R/W

0000

Update NCO Channel 0.

0001

Update NCO Channel 1.

0010

Update NCO Channel 2.

0011

Update NCO Channel 3.

0x0316 DDC0 Phase

Increment 0

[7:0] DDC0 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0317 DDC0 Phase

Increment 1

[7:0] DDC0 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0318 DDC0 Phase

Increment 2

[7:0] DDC0 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0319 DDC0 Phase

Increment 3

[7:0] DDC0 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x031A DDC0 Phase

Increment 4

[7:0] DDC0 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x031B DDC0 Phase

Increment 5

[7:0] DDC0 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x031D DDC0 Phase

Offset 0

[7:0] DDC0 phase

offset[7:0]

Twos complement POW for the NCO.

0x0

R/W

0x031E DDC0 Phase

Offset 1

[7:0] DDC0 phase

offset[15:8]

Twos complement POW for the NCO.

0x0

R/W

0x031F DDC0 Phase

Offset 2

[7:0] DDC0 phase

offset[23:16]

Twos complement POW for the NCO.

0x0

R/W

0x0320 DDC0 Phase

Offset 3

[7:0] DDC0 phase

offset[31:24]

Twos complement POW for the NCO.

0x0

R/W

0x0321 DDC0 Phase

Offset 4

[7:0] DDC0 phase

offset[39:32]

Twos complement POW for the NCO.

0x0

R/W

0x0322 DDC0 Phase

Offset 5

[7:0] DDC0 phase

offset[47:40]

Twos complement POW for the NCO.

0x0

R/W

0x0327 DDC0 test

enable

[7:3] Reserved

Reserved.

0x0

DDC0 Q output test

mode enable

Q samples always use Test Mode B block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

0x0

R/W

Test mode disabled.

Test mode enabled.

Reserved

Reserved.

0x0

DDC0 I output test

mode enable

I samples always use Test Mode A block. The test mode is selected

using the channel dependent Register 0x0550, Bits[3:0].

0x0

R/W

Test mode disabled.

Test mode enabled.

0x0330 DDC1 control

DDC1 mixer select

0x0

R/W

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real, and

imaginary quadrature ADC receive channels; analog

demodulator).

DDC1 gain select

Gain can be used to compensate for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its

negative component.

0x0

R/W

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC1 IF mode

0x0

R/W

Variable IF mode.

0 Hz IF mode.

fS Hz IF mode.

Test mode.

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