AD9689-2000EBZ datasheet(106/134 Pages) AD

106 / 134 page

AD9689

Data Sheet

Rev. A | Page 106 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

DDC next sync

0x0

R/W

Continuous mode. The SYSREF frequency must be an integer

multiple of the NCO frequency for this function to operate

correctly in continuous mode.

Only the next valid edge of the SYSREF± pin is used to synchronize

the NCO in the DDC block. Subsequent edges of the SYSREF± pin are

ignored. When the next SYSREF signal is found, the DDC

synchronization mode bit (Register 0x0300, Bit 0) is cleared.

DDC synchronization

mode

The SYSREF± input pin must be enabled to synchronize the DDCs. 0x0

R/W

Synchronization disabled.

Synchronization enabled. If Register 0x0300, Bit 1 = 1, only the

next valid edge of the SYSREF± pin is used to synchronize the

NCO in the DDC block. Subsequent edges of the SYSREF± pin are

ignored. When the next SYSREF signal is received, this bit is

cleared.

0x0310

DDC0 control

DDC0 mixer select

0x0

R/W

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real, and

imaginary quadrature ADC receive channels; analog

demodulator).

DDC0 gain select

Gain can be used to compensate for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its

negative component.

0x0

R/W

0 dB gain.

6 dB gain (multiply by 2).

[5:4]

DDC0 intermediate

frequency (IF) mode

0x0

R/W

Variable IF mode.

0 Hz IF mode.

fS Hz IF mode.

Test mode.

DDC0 complex to real

enable

0x0

R/W

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra fS mixing

to convert to real.

[2:0]

DDC0 decimation rate

select

Decimation filter selection.

0x0

R/W

000

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

001

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

010

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

011

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

100

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

101

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

110

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

111

Decimation determined by Register 0x0311, Bits[7:4].

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