AD9689-2000EBZ datasheet(102/134 Pages) AD

102 / 134 page

AD9689

Data Sheet

Rev. A | Page 102 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0120 SYSREF Control 1

Reserved

Reserved.

0x0

SYSREF± flag reset

0x0

R/W

Normal flag operation.

SYSREF± flags held in reset (setup/hold error flags cleared).

Reserved

Reserved.

0x0

SYSREF± transition select

0x0

R/W

SYSREF± is valid on low to high transitions using the selected

CLK± edge. When changing this setting, SYSREF± mode select

must be set to disabled.

SYSREF± is valid on high to low transitions using the selected

CLK± edge. When changing this setting, SYSREF± mode select

must be set to disabled.

CLK± edge select

0x0

R/W

Captured on the rising edge of CLK± input.

Captured on the falling edge of CLK± input.

[2:1] SYSREF± mode select

0x0

R/W

Disabled.

Continuous.

N-shot.

Reserved

Reserved.

0x0

0x0121 SYSREF Control 2

[7:4] Reserved

Reserved.

0x0

[3:0] SYSREF N-shot ignore

counter select

0x0

R/W

0000

Next SYSREF± transition only (do not ignore).

0001

Ignore the first SYSREF± transition.

0010

Ignore the first two SYSREF± transitions.

0011

Ignore the first three SYSREF± transitions.

…

1110

Ignore the first 14 SYSREF± transitions.

1111

Ignore the first 15 SYSREF± transitions.

0x0122 SYSREF Control 3

[7:4] Reserved

Reserved.

0x0

[3:2] SYSREF window negative

Negative skew window (measured in sample clocks). Number

of clock cycles before the sample clock by which captured

SYSREF transitions are ignored.

0x0

R/W

No negative skew; SYSREF must be captured accurately.

One sample clock of negative skew.

Two sample clocks of negative skew.

Three sample clocks of negative skew.

[1:0] SYSREF window positive

Positive skew window (measured in sample clocks). Number of

clock cycles before the sample clock by which captured SYSREF

transitions are ignored.

0x0

R/W

No positive skew; SYSREF must be captured accurately.

One sample clock of positive skew.

Two sample clocks of positive skew.

Three sample clocks of positive skew.

0x0123 SYSREF Control 4

Reserved

Reserved.

0x0

[6:0] SYSREF± timestamp

delay, Bits[6:0]

SYSREF± timestamp delay (in converter sample clock cycles).

0x00

R/W

0 sample clock cycle delay.

1 sample clock cycle delay.

…

111 1111 127 sample clock cycle delay.

0x0128 SYSREF Status 1

[7:4] SYSREF± hold status

SYSREF± hold status.

0x0

[3:0] SYSREF± setup status

SYSREF± setup status.

0x0

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