AD9689-2000EBZ datasheet(101/134 Pages) AD

101 / 134 page

Data Sheet

AD9689

Rev. A | Page 101 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x010B Clock divider

SYSREF status

[7:4] Reserved

Reserved.

0x0

[3:0] Clock divider SYSREF

offset

Clock divider phase status (measured in ½ clock cycles). Internal

clock divider phase of the captured SYSREF signal applied to the

phase offset. Only used when Register 0x010A, Bit 7 = 1. When

decimal and Register 0x010A, Bits[1:0] = 0 decimal, clock divider

SYSREF offset = Register 0x0129, Bits[3:0].

0x0

0x0110 Clock delay control [7:3] Reserved

Reserved.

0x0

[2:0] Clock delay mode select

Clock delay mode select. Used in conjunction with

0x0

R/W

000

No clock delay.

010

Fine delay: only 0 to 16 delay steps are valid.

011

Fine delay (lowest jitter): only 0 to 16 delay steps are valid.

100

Fine delay: all 192 delay steps are valid.

110

Fine delay enabled (all 192 delay steps are valid); super fine

delay enabled (all 128 delay steps are valid).

0x0111 Clock super fine

delay (local)

[7:0] Clock super fine delay

adjust

Clock super fine delay adjust. This is an unsigned control to

adjust the super fine sample clock delay in 0.25 ps steps. These

bits are only used when Register 0x0110, Bits[2:0] = 010 or 110.

0x0

R/W

0x00

0 delay steps.

…

0x08

8 delay steps.

…

0x80

128 delay steps.

0x0112 Clock fine delay

(local)

[7:0] Set clock fine delay

Clock fine delay adjust. This is an unsigned control to adjust the

fine sample clock skew in 1.725 ps steps. These bits are only

used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6.

Minimum = 0. Maximum = 192. Increment = 1. Unit is delay steps.

0xC0 R/W

0x00

0 delay steps.

…

0x08

8 delay steps.

…

0xC0

192 delay steps.

0x011B Clock status

[7:1] Reserved

Reserved.

0x0

Input clock detect

Clock detection status.

0x0

Input clock not detected.

Input clock detected/locked.

0x011C Clock Duty Cycle

Stabilizer 1 control

(local)

[7:2] Reserved

Reserved.

0x0

R/W

DCS1 enable

Clock DCS1 enable.

0x1

R/W

DCS1 bypassed.

DCS1 enabled.

DCS1 power up

Clock DCS1 power-up.

0x1

R/W

DCS1 powered down.

DCS1 powered up.

0x011E Clock Duty Cycle

Stabilizer 2 control

[7:2]

Reserved

Reserved.

0x0

R/W

DCS2 enable

Clock DCS2 enable.

0x1

R/W

DCS2 bypassed.

DCS2 enabled.

DCS2 power up

Clock DCS2 power-up.

0x1

R/W

DCS2 powered down.

DCS2 powered up.

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