TMP88CU74F datasheet(29/132 Pages) TOSHIBA

29 / 132 page

TMP88CU74

2003-02-17

88CU74-29

(0003C, 0003DH)

IL15

IL14

IL13

IL12

IL11

IL10

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

(Initial Value: 00000000 000000

**)

EF15 EF14 EF13 EF12 EF11 EF10

EF9

EF8

EF7

EF6

EF5

EF4

IMF

EIR

(0003A, 0003BH)

(Initial Value: 00000000 0000

***0)

Note 1: Do not use any read-modify-write instruction such as bit manipulation for clearing IL.

Note 2: Do not set IMF to “1” during non-maskable interrupt service program.

Note 3: Bits1 and 0 in ILL are read in as undefined data when a read instruction is executed.

Note 4:

*: Don’ t care

Figure 1.5.2 Interrupt latch (IL) and interrupt enable register (EIR)

1.5.1

Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is

cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 12

machine cycles (3.84

μs at fc = 12.5 MHz in the NORMAL mode) after the completion of the

current instruction execution. The interrupt service task terminates upon execution of an

interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo

non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance

processing.

(1) Interrupt acceptance

Interrupt acceptance processing is as follows.

The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the

acceptance of any following maskable interrupts. When a non-maskable interrupt

is accepted, the acceptance of any following interrupts is temporarily disabled.

The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.

The contents of the program counter (return address) and the program status

word (PSW) are saved (pushed) on the stack in sequence of PSWH, PSWL, PCE,

PCH, PCL. The stack pointer (SP) is decremented five times.

The entry address of the interrupt service program is read from the vector table,

and set to the program counter.

The RBS control code is read from the vector table. The lower 4-bit of this code is

added to the RBS.

The instruction stored at the entry address of the interrupt service program is

executed.

ILH (0003DH)

ILL (0003CH)

EIRL (0003AH)

EIRH (0003BH)

2007-10-19

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