TMP88CU74F datasheet(78/132 Pages) TOSHIBA

78 / 132 page

TMP88CU74

2003-02-17

88CU74-78

2.9.2

Control

The timer/counter 4 is controlled by a timer/counter 4 control register (TC4CR) and an

8-bit timer register 4 (TREG4). Reset does not affect TREG4.

TREG4

(0001BH)

Write only

TC4CR

(0001CH)

TFF4

“0”

TC4S

TC4CK

TC4M

(Initial value: 00

*0 0000 )

TC4M

TC4 operating mode select

00: Timer

01: Reserved

10: Programmable divider output (PDO) mode

11: Pulse width modulation (PWM) output mode

NORMAL1/2, IDLE1/2 mode

DV7CK

= 0

DV7CK

= 1

DV1CK

= 0 DV1CK = 1 DV1CK = 0 DV1CK = 1

SLOW,

SLEEP

mode

fc/2

fs/2

fc/2

⎯

fc/2

⎯

TC4CK

TC4 source clock select [Hz]

Reserved

TC4S

TC4 start control

0: Stop and counter clear

1: Start

TFF4

Timer F/F4 control

00: Clear

01: Reserved

10: Reserved

11:

⎯ (Note 3)

Write

only

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz],

*: Don’t care

Note 2: Set the operating mode, the source clock selection, the edge selection (INT4ES) and timer F/F4 control when

the TC4 stops (TC4S = 0)

Note 3: Set TFF4 to “11” in the timer and event counter mode and PWM mode.

Note 4: Values to be loaded to the timer register must satisfy the following condition.

0<TREG4 in others

Note 5: TC4CR is a write-only register and must not be used with any of the read-modify-write instructions such as SET,

CLR, etc.

Figure 2.9.2 Timer Register 4 and TC4 Control Register

2.9.3

Function

The timer/counter 4 has four operating modes: timer, event counter, programmable

divider output, and PWM output mode.

(1) Timer mode

In this mode, the internal clock is used for counting up. The contents of TREG4 are

compared with the contents of up-counter. If a match is found, an INTTC4 interrupt is

generated and the up-counter is cleared to “0”. Counting up resumes after the

up-counter is cleared.

2007-10-19

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