TMP88CU74F datasheet(11/132 Pages) TOSHIBA

11 / 132 page

TMP88CU74

2003-02-17

88CU74-11

DVCR

(00030H)

“0”

DV1CK

(Initial value:

**0* ****)

DV1CK

Selection of input clock to the

1st stage of the divider

0: fc/4

1: fc/8

R/W

Note 1: fc: High-frequency clock [Hz],

*: Don't care

Note 2: Bit 4 to 0 in CGCR is always read in as “1” when a read instruction is executed.

Figure 1.4.4 Clock Gear Control Register

TBTCR

(00036H)

(DVOEN)

(DVOCK)

DV7CK (TBTEN)

(TBTCK)

(Initial value: 0

**0 0***)

DV7CK

Selection of input clock to the

7 th stage of the divide

0: fc/2

8 or fc/29 [Hz]

1: fs

R/W

Note 1: fc: High-frequency clock [Hz],

*: Don't care

Note 2: Do not set DV7CK to “1” in the single clock mode.

Note 3: Do not set DV7CK to “1” before low-frequency clock is stable in the dual-clock mode.

Figure 1.4.5 Timing Generator Control Register

(2) Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the

main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a

total of 15 different types of instructions for the TLCS-870/X Series: ranging from

1-cycle instructions which require one machine cycle for execution to 15-cycle

instructions which require 15 machine cycles for execution.

A machine cycle consists of 4 states (S0 to S3), and each state consists of one main

system clock.

Figure 1.4.6 Machine Cycle

1.4.3

Stand-by Controller

The stand-by controller starts and stops the oscillation circuits for the high-frequency

and low-frequency clocks, and switches the main system clock. There are two operating

modes: single-clock and dual-clock. These modes are controlled by the system control

registers (SYSCR1and SYSCR2).

Figure 1.4.7 shows the operating mode transition diagram and Figure 1.4.8 shows the

system control registers.

(1) Single-clock mode

Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and

P22 (XTOUT) pins are used as input/output ports. In the single-clock mode, the

machine cycle time is 4/fc [s] (0.32

μs at fc = 12.5 MHz).

Main system clock

(fm)

State

0.32

μs at fc = 12.5 MHz

122

μs at fs = 32.8 kHz

1/fc or 1/fs [s]

Machine cycle

2007-10-19

TMP88CU74F bảng dữ liệu(PDF) 11 Page - Toshiba Semiconductor

TMP88CU74F bảng dữ liệu(HTML) 11 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL