| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
TMP88CU74F bảng dữ liệu(PDF) 37 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP88CU74F bảng dữ liệu(HTML) 37 Page - Toshiba Semiconductor |
|
37 / 132 page ![]() TMP88CU74 2003-02-17 88CU74-37 1.6 Reset Circuit The TMP88CU74 has four types of reset generation procedures: an external reset input, an address trap reset output, a watchdog timer reset output and a system clock reset output. Table 1.6.1 shows on-chip hardware initialization by reset action. The malfunction reset output circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. The RESET pin can output level “L” at the maximum 24/fc [s] (1.92 μs at 12.5 MHz) when power is turned on. Table 1.6.1 Initializing Internal Status by Reset Action On-chip Hardware Initial Value On-chip Hardwear Initial Value Program counter (PC) (FFFFEH to FFFFCH) Stack pointer (SP) Not initialized General-purpose registers (W, A, B, C, D, E, H, L) Not initialized Prescaler and Divider of timing generator 0 Register bank selector (RBS) 0 Jump status flag (JF) 1 Watchdog timer Enable Zero flag (ZF) Not initialized Carry flag (CF) Not initialized Half carry flag (HF) Not initialized Sign flag (SF) Not initialized Overflow flag (VF) Not initialized Interrupt master enable flag (IMF) 0 Output latches of I/O ports Refer to I/O port circuitry Interrupt individinal enable flags (EF) 0 Interrupt latchs (IL) 0 Control registers Refer to each of control register 1.6.1 External Reset Input The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFFC to FFFFEH. Figure 1.6.1 Reset Circuit VDD Reset input RESET Sink open drain Watchdog timer reset Address trap reset System clock reset Malfunction reset output circuit 2007-10-19 |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |