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TMP88CU74F bảng dữ liệu(PDF) 76 Page - Toshiba Semiconductor |
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TMP88CU74F bảng dữ liệu(HTML) 76 Page - Toshiba Semiconductor |
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76 / 132 page ![]() TMP88CU74 2003-02-17 88CU74-76 (3) Capture mode The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing AC 50/60 Hz, etc. The counter is free running by the internal clock. On the rising (falling) edge of the TC3 pin input, the current contents of counter is loaded into TREG3A, then the up-counter is cleared to “0” and an INTTC4 interrupt is generated. On the falling (rising) edge of the TC3 pin input, the current contents of the counter is loaded into TREG3B. In this case, counting continues. On the next rising (falling) edge of the TC3 pin input, the current contents of counter are loaded into TREG3A, then the counter is cleared again and an interrupt is generated. If the counter overflows before the edge is detected. FFH is set into TREG3A, and the counter is cleared and an INTTC3 interrupt is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is FFH. Also, after an interrupt (capture to TREG3A, or overflow detection) is generated, capture and overflow detection are halted until TREG3A has been read out; however, the counter continues. As reading out TREG3A resumes capture/overflow detection, TREG3B must be beforehand read out. Figure 2.8.3 Capture Mode Timing Chart (at INT4ES = 0) m −1 Source clock Up-counter TC3 pin input TREG3A k − 2 n m m +1 n −1 0 n 1 2 3 0 Overflow FF (Overflow) k −1 k 0 1 1 2 3 FE FF m k FE Capture Capture TREG3B INTTC3 interrupt Reading TREG3A 2007-10-19 |
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