| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
TMP88CU74F bảng dữ liệu(PDF) 71 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP88CU74F bảng dữ liệu(HTML) 71 Page - Toshiba Semiconductor |
|
71 / 132 page ![]() TMP88CU74 2003-02-17 88CU74-71 2.7.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. Also timer/counter 2 is used for warm-up when switching from SLOW mode to NORMAL2 mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TREG2 are compared with the contents of up-counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Also, when “fcgck” is selected as the source clock during SLOW mode, the lower 11 bits of TREG2 are ignored and an INTTC2 interrupt is generated by matching the upper 5 bits. Thus, in this case, only the TREG2H setting is necessary. Table 2.7.1 Source Clock (Internal clock) for Timer/Counter 2 (at fc = 12.5 MHz, fs = 32.8 kHz) NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 DV1CK = 0 DV1CK = 1 DV1CK = 0 DV1CK = 1 TC2CK Resolution Maximum Time Setting Resolution Maximum Time Setting Resolution Maximum Time Setting Resolution Maximum Time Setting 000 001 010 011 100 101 671 ms 655.36 μs 20.48 μs 0.64 μs − 30.5 μs 12.2 h 43.0 s 1.34 s 41.92 ms − 2 s 1.34 s 1.31 ms 40.96 μs 1.28 μs − 30.5 μs 24.4 h 1.4 min 2.7 s 83.8 ms − 2 s 1 s 0.98 ms 16 μs 0.5 μs − 30.5 μs 18.2 h 1.07 min 1.05 s 32.75 ms − 2 s 1 s 0.98 ms 32 μs 1 μs − 30.5 μs 18.2 h 1.07 min 2.1 s 65.5 ms − 2 s SLOW Mode SLEEP Mode TC2CK Resolution [s] Maximum Time Setting Resolution [s] Maximum Time Setting 000 001 01 * 100 110 101 1 s 0.98 ms − 125 ns (Note) 160 ns (Note) − 18.2 h 1.07 min − − − − 1 s 0.98 ms − − − − 18.2 h 1.07 min − − − − Note: fc and fc/2 can be used only in the timer mode. It is used for warm-up when switching from SLOW mode to NORMAL2 mode. (at fc = 8 MHz, TC2CK = <100>) Example: Sets the timer mode with source clock fc/2 4 [Hz] and generates an interrupt every 25 ms (at fc = 12.5 MHz, DV1CK = 1). LDW (TREG2), 4C46H ; Sets TREG2 (25 ms ÷ 2 4/fc = 4C46H) SET (EIRH). EF14 ; Enables INTTC2 interrupt EI LD (TC2CR), 00101100B ; Starts TC2 2007-10-19 |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |