TMP88CU74F datasheet(56/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-56

2.4.2

Watchdog Timer Control

Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The

watchdog timer is automatically enabled after reset.

(1) Malfunction detection methods using the watchdog timer

The CPU malfunction is detected at follows.

Setting the detection time, selecting output, and clearing the binary counter.

Repeatedly clearing the binary counter within the setting detection time

If the CPU malfunctions such as endless looping or deadlock occur for any cause, the

watchdog timer output will become active at the rising of an overflow from the binary

counters unless the binary counters are cleared. At this time, when WDTOUT = 1 a

reset is generated, which drives the RESET pin low to reset the internal hardware and

the external circuit. When WDTOUT = 0, a watchdog timer interrupt(INTWDT) is

generated.

The watchdog timer temporarily stops counting in STOP mode including warm-up or

IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE

mode is released.

Note:

Just right before disabling the watchdog timer, disable the acceptance of interrupts

(DI) and clear the watchdog timer.

If the watchdog timer is disabled under conditions other than the above, the proper

operation cannnot be guaranteed.

Example:

;

Disable interrupt acceptance.

(WDTCR2), 4EH

;

Clears the watchdog timer.

LDW

(WDTCR1), B100H

;

Disables the watchdog timer.

;

Enables interrupt acceptance.

Example: Sets the watchdog timer detection time to 2

21/fc [s] and resets the CPU malfunction.

(WDTCR2), 4EH

;

Clears the binary counters

(WDTCR1), 00001101B

;

WDTT

← 10, WDTOUT ← 1

Within WDT

detection

time

(WDTCR2), 4EH

;

Clears the binary counters (always clear

immediately after changing WDTT)

(WDTCR2), 4EH

;

Clears the binary counters

Within WDT

detection

time

(WDTCR2), 4EH

;

Clears the binary counters

2007-10-19

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