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TMP88CU74F bảng dữ liệu(PDF) 87 Page - Toshiba Semiconductor |
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TMP88CU74F bảng dữ liệu(HTML) 87 Page - Toshiba Semiconductor |
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87 / 132 page ![]() TMP88CU74 2003-02-17 88CU74-87 (6) Transmitter/Receiver selection Set the TRX (bit 6 in SBICR2) to “1” for operating the TMP88CU74 as a transmitter. Reset the TRX for operation as a receiver. When data with an addressing format is transferred in the slave mode, the TRX is set to “1” if the direction bit (R/ W ) sent from the master device is “1”, and is cleared to “0” if the bit is “0”. In the master mode, after an acknowledge signal is returned from the slave device with the hardware, the TRX is set to “0” if a transmitted direction bit is “1”, and set to “1” if it is “0”. When an acknowledge signal is not returned, the current condition is maintained. The TRX is cleared to “0” by the hardware after a stop condition on the bus is detected or arbitration is lost. The following table shows TRX changing conditions and TRX value after changing. Mode Direction Bit Conditions TRX after Changing 0 0 Slave mode 1 When the received slave address is the same as I 2CAR 1 0 1 Master mode 1 When the ACK signal is returned 0 When the serial bus interface circuit is used with a free data format, the TRX is not changed by hardware since the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (7) Start/Stop condition generation A start condition and 8-bit data are output on the bus by writing “1” to the MST, TRX and BB when the BB (bit 5 in SBICR2) is “0”. It is necessary to set the transmitting data to the data buffer register and “1” to ACK beforehand. Figure 2.10.7 Start Condition Generation and Slave Address Generation When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX, and PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is generated on a bus. Figure 2.10.8 Stop Condition Generation SCL pin SDA pin Start condition slave address and the direction bit Acknowledge signal 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A2 A1 A0 R/W SDA pin SCL pin Stop condition 2007-10-19 |
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