TMP88CU74F datasheet(34/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-34

(3) Interrupt return

The interrupt return instructions [RETI]/[RETN] perform the following operations.

[RETI] Maskable interrupt return

[RETN] Non-maskable interrupt return

1. The contents of the program counter and the

program status word are restored from the

stack.

2. The stack pointer is incremented 5 times.

3. The interrupt master enable flag is set to “1”.

4. The interrupt nesting counter is decremented,

and the interrupt nesting flag is changed.

1. The contents of the program counter and

program status word are restored from the

stack.

2. The stack pointer is incremented 5 times.

3. The interrupt master enable flag is set to “1” only

when a non-maskable interrupt is accepted in

interrupt enable status. However, the interrupt

master enable flag remains at “0” when so clear

by an interrupt service program.

4. The interrupt nesting counter is decremented,

and the interrupt nesting flag is changed.

Interrupt requests are sampled during the final cycle of the instruction being

executed. Thus, the next interrupt can be accepted immediately after the interrupt

return instruction is executed.

Note:

When the interrupt processing time is longer than the interrupt request generation

time, the interrupt service task is performed but not the main task.

1.5.2

Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts

interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a

non-maskable interrupt is already underway, executing the SWI instruction will not

generate a software interrupt but will result in the same operation as the [NOP]

instruction.

Use the [SWI] instruction only for detection of the address error or for debugging.

Note:

To use the SWI instruction for software break in the development tool, software interrupt

always generates even if the non-maskable interrupt is in progress.

Address error detection

FFH is read if for some cause such as noise the CPU attempts to fetch an instruction

from a non-existent memory address. Code FFH is the SWI instruction, so a software

interrupt is generated and an address error is detected. The address error detection

range can be further expanded by writing FFH to unused areas of the program memory.

Address-trap reset is generated in case that an instruction is fetched from RAM or SFR

areas.

Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software

break point setting address.

2007-10-19

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