TMP88CU74F datasheet(41/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-41

Figure 2.2.1 Input/Output Timing (Example)

When reading an I/O port except programmable I/O ports P0 and P1, whether the pin input

data or the output latch contents are read depends on the instructions, as shown below:

(a) Instructions that read the output latch contents

XCH r, (src)

CLR/SET/CPL (src).b

CLR/SET/CPL (pp).g

LD (src).b, CF

LD (pp).b, CF

XCH CF, (src), b

ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n

(src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)

MXOR (src), m

(b) Instructions that read the pin input data

(HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL)

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Fetch cycle

Read cycle

Ex.: LD A, (x)

(a) Input timing

Instruction

execution

cycle

Input strobe

Data input

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Fetch cycle

Write cycle

Ex.: LD (x) , A

Instruction

execution

cycle

Output latch

pulse

Data output

(b) Output timing

Note: The positions of the read and write cycles may vary, depending on the instruction.

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2007-10-19

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