TMP88CU74F datasheet(63/132 Pages) TOSHIBA

63 / 132 page

TMP88CU74

2003-02-17

88CU74-63

Figure 2.6.3 Timer Mode Timing Chart

(2) External trigger timer mode

In this mode, counting up is started by an external trigger. This trigger is the edge of

the TC1 pin input. Either the rising or falling edge can be selected with INT2ES in

EINTCR. Edge selection is the same as for INT3 pin. Source clock is an internal clock

selected with TC1CK. The contents of TREG1A is compared with the contents of

up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is

cleared to “0” and halted. The counter is restarted by the selected edge of the TC1 pin

input.

When METT1 (bit 6 in TC1CR) is “1”, inputting the edge to the reverse direction of

the trigger edge to start counting clears the counter, and the counter is stopped.

Inputting a constant pulse width can generate interrupts. When METT1 is “0”, the

reverse directive edge input is ignored. The TC1 pin input edge before a match

detection is also ignored.

The TC1 pin input has the same noise rejection as the INT3 pin; therefore, pulses of

7/fc [s] or less are rejected as noise. A pulse width of 24/fc [s] or more is required for

edge detection in NORMAL1, 2 or IDLE1, 2 mode. The noise rejection circuit is turned

off in SLOW and SLEEP modes. But, a pulse width of one machine cycle or more is

required.

Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100

μs later. (at fc = 12.5 MHz,

DV1CK

= 1)

(EINTCR), 00000000B

;

INT3ES

← 0 (rising edge)

LDW

(TREG1A), 004EH

;

100

μs ÷ 2

4/fc = 4EH

SET

(EIRL).EF4

;

INTTC1 interrupt enable

(TC1CR), 00111000B

;

TC1 external trigger start, METT1

= 0

TREG1B

− 1

− 2

Up-counter

SCAP1

Capture

+ 1

+ 2

(b) Software capture

TREG1A

INTTC1 interrupt

− 1

+ 1

Capture

Command start

Source clock

Up-counter

Source clock

− 1 n 0

Match detect

Counter clear

(a) Timer mode

2007-10-19

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