TMP88CU74F datasheet(72/132 Pages) TOSHIBA

72 / 132 page

TMP88CU74

2003-02-17

88CU74-72

(2) Event counter mode

In this mode, events are counted on the rising edge of the TC2 pin input. The

contents of TREG2 are compared with the contents of the up-counter. If a match is

found, an INTTC2 interrupt is generated, and the counter is cleared. The maximum

frequency applied to the TC2 pin is shown in Table 2.7.2. Two or more machine cycles

are required for both the “H” and “L” levels of the pulse width.

Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.

LDW

(TREG2), 640

;

Sets TREG2

SET

(EIRH). EF14

;

Enables INTTC2 interrupt

(TC2CR), 00111100B

;

Starts TC2

Table 2.7.2 Timer/Counter 2 External Clock Source

Maximum Applied Frequency [Hz]

NORMAL1/2, IDLE1/2 Mode

SLOW, SLEEP Mode

fc/2

fs/2

(3) Window mode

In this mode, counting up is performed on the rising edge of an internal clock during

TC2 external pin input(window pulse) is “H” level. The contents of TREG2 are

compared with the contents of up-counter. If a match is found, an INTTC2 interrupt is

generated, and the up-counter is cleared.

The maximum applied frequency (TC2 input) must be considerably slower than the

selected internal clock.

Example: Generates an interrupt, inputting “H” level pulse width of 120 ms or more. (at fc = 12.5 MHz,

DV1CK = 1)

LDW

(TREG2), 0056H

;

Sets TREG2 (120 ms

÷ 2

14/fc = 0056H)

SET

(EIRH). EF14

;

Enables INTTC2 interrupt

(TC2CR), 00100101B

;

Starts TC2

Figure 2.7.3 Window Mode Timing Chart

INTTC2 interrupt

TREG2

− 3n − 2

− 1

Match detect

Counter clear

TC2 pin input

Internal clock

Up-counter

2007-10-19

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