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TMP88CU74F bảng dữ liệu(PDF) 92 Page - Toshiba Semiconductor |
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TMP88CU74F bảng dữ liệu(HTML) 92 Page - Toshiba Semiconductor |
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92 / 132 page ![]() TMP88CU74 2003-02-17 88CU74-92 (3) 1-word data transfer Check the MST by the INTSBI interrupt process after a 1-word data transfer is completed, and determine whether the mode is a master or slave. a. When the MST is “1” (Master mode) Check the TRX and determine whether the mode is a transmitter or receiver. 1. When the TRX is “1” (Transmitter mode) Check the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to generate a stop condition and terminate data transfer. When the LRB is “0”, the receiver requests new data. When the next transmitted data is other than 8 bits, set the BC and write the transmitted data to the SBIDBR after setting ACK to “1”. After writing the data, the PIN becomes “1”, a serial clock pulse is generated for transferring a new 1-word of data from the SCL pin, and then the 1-word data is transmitted. After the data is transmitted, an INTSBI interrupt request occurs. The PIN becomes “0” and the SCL pin is pulled down to the low level. If the data to be transferred is more than one word in length, repeat the procedure from the LRB checking above. Figure 2.10.12 Example when BC = “000”, ACK = “1” 2. When the TRX is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set the BC again. Set the ACK to “1” and read the received data from the SBIDBR (data which is read immediately after a slave address is sent is undefined). After the data is read, the PIN becomes “1”. The TMP88CU74 outputs a serial clock pulse to the SCL to transfer new 1-word of data and sets the SDA pin to “0” at the acknowledge signal timing. An INTSBI interrupt request occurs and the PIN becomes “0”. The TMP88CU74 outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR. Figure 2.10.13 Example when BC = “000”, ACK = “1” SCL pin SDA pin Acknowledge signal to a transmitter 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 PIN INTSBI interrupt request D0 Read SBIDBR New D7 SCL pin SDA pin Acknowledge signal from a receiver 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 PIN INTSBI interrupt request D0 Write to SBIDBR 2007-10-19 |
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