TMP88CU74F datasheet(98/132 Pages) TOSHIBA

98 / 132 page

TMP88CU74

2003-02-17

88CU74-98

Figure 2.10.20 Shift Edge

(2) Transfer mode

The SIOM (bits 5 and 4 in SIO1CR) is used to select a transmit, receive, or

transmit/receive mode.

8-bit transmit mode

Set a control register to a transmit mode and write data to the SBIDBR.

After the data is written, set the SIOS to “1” to start data transfer. The

transmitted data is transferred from the SBIDBR to the shift register and output

to the SO0 pin in synchronous with the serial clock, starting from the least

significant bit (LSB). When the data is transferred to the shift register, the

SBIDBR becomes empty. The INTSBI (buffer empty) interrupt request is

generated to request new data.

When the internal clock is used, the serial clock will stop and automatic-wait

function will be initiated if new data is not loaded to the data buffer register after

the specified 8-bit data is transmitted. When new data is written, automatic-wait

function is canceled.

When the external clock is used, data should be written to the SBIDBR before

new data is shifted. The transfer speed is determined by the maximum delay time

between the time when an interrupt request is generated and the time when data

is written to the SBIDBR by the interrupt service program.

When the transmit is started, the same value as the final bit of the last data is

output until the falling edge of the SCK after the SIOF goes “1”.

Transmitting data is ended by cleaning the SIOS to “0” by the buffer empty

interrupt service program or setting the SIOINH to “1”. When the SIOS is cleared,

the transmitted mode ends when all data is output. In order to confirm if data is

surely transmitted by the program, set the SIOF (bit 3 in the SBISR) to be sensed.

The SIOF is cleared to “0” when transmitting is complete. When the SIOINH is

set, transmitting data stops. The SIOF turns “0”.

When the external clock is used, it is also necessary to clear the SIOS to “0”

before new data is shifted; otherwise, dummy data is transmitted and operation

ends.

SCK

SO0 pin

Shift register

SCK

SI0 pin

Shift register

Bit 0

Bit 1

(a) Leading edge

(b) Trailing edge

********

76543210

*7654321

**765432

***76543

****7654

*****765

******76

*******7

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

*******

******

210

*****

3210

****

43210

***

543210

6543210

* 76543210

*: Don’t care

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

2007-10-19

TMP88CU74F bảng dữ liệu(PDF) 98 Page - Toshiba Semiconductor

TMP88CU74F bảng dữ liệu(HTML) 98 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL