TMP88CU74F datasheet(14/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-14

System Control Register 1

SYSCR1

(00038H)

STOP

RELM

RETM

“1”

WUT

(Initial value: 0000 00

**)

STOP

STOP mode start

0: CPU core and peripherals remain active

1: CPU core and peripherals are halted (start STOP mode)

RELM

Release method

for STOP mode

0: Edge-sensitive release

1: Level-sensitive release

RETM

Operating mode

after STOP mode

0: Return to NORMAL mode

1: Return to SLOW mode

Return to NORMAL mode

DV1CK

= 0

DV1CK

= 1

Return to

SLOW mode

× 2

16/fc

× 2

17/fc

× 2

13/fc

16/fc

17/fc

13/fc

× 2

14/fc

× 2

15/fc

⎯

WUT

Warming-up time at releasing

STOP mode

14/fc

15/fc

⎯

R/W

Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when

transiting from SLOW mode to STOP mode.

Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the

RETM contents.

Note 3: fc: High-frequency clock [Hz]

fs: Low-frequency clock [Hz]

*: Don’t care

Note 4: Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.

Note 5: Always set bit 4 in SYSCR1 to “1” when STOP mode is started.

System Control Register 2

SYSCR2

(00039H)

XEN

XTEN

SYSCK

IDLE

(Initial value: 1000

****)

XEN

High-frequency oscillator

control

0: Turn off oscillation

1: Turn on oscillation

XTEN

Low-frequency oscillator

control

0: Turn off oscillation

1: Turn on oscillation

SYSCK

Main system clock select

(write)/main system clock

monitor (read)

0: High-frequency clock

1: Low-frequency clock

IDLE

IDLE mode start

0: CPU and watchdog timer remain active

1: CPU and watchdog timer are stopped (start IDLE1 mode)

R/W

Note 1: XEN and SYSCK are automatically overwritten in accordance with the contents of RETM (bit 5 in SYSCR1)

when STOP mode is released.

RETM

Operating mode after STOP mode

XTEN

SYSCK

NORMAL 1/2 mode

SLOW mode

Note 2: Do not clear XEN to “0” when SYSCK = 0, and do not clear XTEN to “0” when SYSCK = 1.

Note 3: A reset is applied ( RESET pin output goes low) if both XEN and XTEN are cleared to “0”.

Note 4:

*: Don’t care

Note 5: Bits 3 to 0 in SYSCR2 are always read in as “1” when a read instruction is executed.

Figure 1.4.8 System Control Registers

2007-10-19

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