HCS08 datasheet(240/290 Pages) MOTOROLA

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MC9S08GB/GT

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by the target BDC clock rate. All communication is initiated and controlled by the host which drives a

high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant

bit first (MSB first). For a detailed description of the communications protocol, refer to 15.3.2

Communication Details.

If a host is attempting to communicate with a target MCU which has an unknown BDC clock rate, a SYNC

command may be sent to the target MCU to request a timed sync response signal from which the host can

determine the correct communication speed.

BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.

Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external

capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively

driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.

Refer to 15.3.2 Communication Details for more detail.

When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD

chooses normal operating mode. When a development system is connected, it can pull both BKGD and

RESET low, release RESET to select active background mode rather than normal operating mode, then

release BKGD. It is not necessary to reset the target MCU to communicate with it through the background

debug interface.

15.3.2 Communication Details

The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to

indicate the start of each bit time. The external controller provides this falling edge whether data is

transmitted or received.

BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data

is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if

512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress

when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU

system.

The custom serial protocol requires the debug pod to know the target BDC communication clock speed.

The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the

BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.

The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams

show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but

asynchronous to the external host. The internal BDC clock signal is shown for reference in counting

cycles.

HCS08 bảng dữ liệu(PDF) 240 Page - Motorola, Inc