| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
HCS08 bảng dữ liệu(PDF) 169 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
HCS08 bảng dữ liệu(HTML) 169 Page - Motorola, Inc |
|
169 / 290 page ![]() Data Sheet — MC9S08GB60/D V1.5 MOTOROLA 169 MC9S08GB/GT CHnIE — Channel n Interrupt Enable This read/write bit enables interrupts from channel n. Reset clears the CHnIE bit. 1 = Channel n interrupt requests enabled. 0 = Channel n interrupt requests disabled (use software polling). MSnB — Mode Select B for TPM Channel n When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 10-3. MSnA — Mode Select A for TPM Channel n When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output compare mode. Refer to Table 10-3 for a summary of channel mode and setup controls. If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. ELSnB:ELSnA — Edge/Level Select Bits Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 10-3, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Table 10-3 Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration XXX 00 Pin not used for TPM channel; use as an external clock for the TPM or revert to general-purpose I/O 0 00 01 Input capture Capture on rising edge only 10 Capture on falling edge only 11 Capture on rising or falling edge 01 01 Output compare Toggle output on compare 10 Clear output on compare 11 Set output on compare 1X 10 Edge-aligned PWM High-true pulses (clear output on compare) X1 Low-true pulses (set output on compare) 1XX 10 Center-aligned PWM High-true pulses (clear output on compare-up) X1 Low-true pulses (set output on compare-up) |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |