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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HCS08 bảng dữ liệu(PDF) 126 Page - Motorola, Inc |
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HCS08 bảng dữ liệu(HTML) 126 Page - Motorola, Inc |
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126 / 290 page  Central Processor Unit (CPU) MC9S08GB/GT 126 MOTOROLA STA opr8a STA opr16a STA oprx16,X STA oprx8,X STA ,X STA oprx16,SP STA oprx8,SP Store Accumulator in Memory M ← (A) 0 –– – DIR EXT IX2 IX1 IX SP2 SP1 B7 C7 D7 E7 F7 9ED7 9EE7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 STHX opr8a STHX opr16a STHX oprx8,SP Store H:X (Index Reg.) (M:M + $0001) ← (H:X) 0 –– – DIR EXT SP1 35 96 9EFF dd hh ll ff 4 5 5 STOP Enable Interrupts: Stop Processing Refer to MCU Documentation I bit ← 0; Stop Processing –– 0 ––– INH 8E 2+ STX opr8a STX opr16a STX oprx16,X STX oprx8,X STX ,X STX oprx16,SP STX oprx8,SP Store X (Low 8 Bits of Index Register) in Memory M ← (X) 0 –– – DIR EXT IX2 IX1 IX SP2 SP1 BF CF DF EF FF 9EDF 9EEF dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 SUB #opr8i SUB opr8a SUB opr16a SUB oprx16,X SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP Subtract A ← (A) – (M) –– IMM DIR EXT IX2 IX1 IX SP2 SP1 A0 B0 C0 D0 E0 F0 9ED0 9EE0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (X); SP ← (SP) – $0001 Push (A); SP ← (SP) – $0001 Push (CCR); SP ← (SP) – $0001 I ← 1; PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte –– 1 ––– INH 83 11 TAP Transfer Accumulator to CCR CCR ← (A) INH 84 1 TAX Transfer Accumulator to X (Index Register Low) X ← (A) –––––– INH 97 1 TPA Transfer CCR to Accumulator A ← (CCR) –––––– INH 85 1 TST opr8a TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Test for Negative or Zero (M) – $00 (A) – $00 (X) – $00 (M) – $00 (M) – $00 (M) – $00 0 –– – DIR INH INH IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 4 1 1 4 3 5 TSX Transfer SP to Index Reg. H:X ← (SP) + $0001 –––––– INH 95 2 TXA Transfer X (Index Reg. Low) to Accumulator A ← (X) –––––– INH 9F 1 TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 –––––– INH 94 2 WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU –– 0 –– – INH 8F 2+ NOTES: 1. Bus clock frequency is one-half of the CPU clock frequency. Table 7-1 HCS08 Instruction Set Summary (Sheet 6 of 6) Source Form Operation Description Effect on CCR VH I N Z C |
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