HCS08 datasheet(272/290 Pages) MOTOROLA

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Electrical Characteristics

MC9S08GB/GT

272

MOTOROLA

Ideal resolution (1 LSB)(5)

RES

2.08V < VDDAD < 3.6V

2.031

—

3.516

1.80V < VDDAD < 2.08V

1.758

—

2.031

Differential non-linearity(6)

DNL

1.80V < VDDAD < 3.6V

—

+0.5

+1.0

LSB

Integral non-linearity(7)

INL

1.80 V < VDDAD < 3.6V

—

+0.5

+1.0

LSB

Zero-scale error(8)

EZS

1.80V < VDDAD < 3.6V

—

+0.4

+1.0

LSB

Full-scale error(9)

EFS

1.80V < VDDAD < 3.6V

—

+0.4

+1.0

LSB

Input leakage error (10)

EIL

1.80V < VDDAD < 3.6V

—

+0.05

LSB

Total unadjusted

error(11)

ETU

1.80V < VDDAD < 3.6V

—

+1.1

+2.5

LSB

NOTES:

1. All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching)

and that adequate low-pass filtering is present on analog input pins (filter with 0.01

µF to 0.1 µF capacitor between analog

input and VREFL). Failure to observe these guidelines may result in system or microcontroller noise causing accuracy

errors which will vary based on board layout and the type and magnitude of the activity.

2. This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single

conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to

starting the conversion and setting the CCF flag. The total conversion time in Bus Cycles for a conversion is:

SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2

CC Bus Cycles = ((PRS+1)*2) * (28)

3. RAS is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may

not fully charge the input circuitry of the ATD resulting in accuracy error.

4. Analog input must be between VREFL and VREFH for valid conversion. Values greater than VREFH will convert to $3FF less

the full scale error (EFS).

5. The resolution is the ideal step size or 1LSB = (VREFH–VREFL)/1024

6. Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current

code width is the difference in the transition voltages to and from the current code.

7. Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition

voltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((VREFH+EFS)–(VREFL+EZS))).

8. Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The

Ideal transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).

9. Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal

transition voltage to a given code is (Code–1/2)*(1/(VREFH–VREFL)).

10. Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog

pin. Reducing the impedance of the network reduces this error.

11. Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight-line

transfer function. This measure of error includes inherent quantization error (1/2LSB) and circuit error (differential,

integral, zero-scale, and full-scale) error. The specified value of ET assumes zero EIL (no leakage or zero real source

impedance).

Table A-7 ATD Timing/Performance Characteristics(1) (Continued)

Num

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

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