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HCS08 bảng dữ liệu(PDF) 130 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 130 Page - NXP Semiconductors |
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130 / 316 page ![]() Analog-to-Digital Converter (S08ADCV1) MC9S08SG8 MCU Series Data Sheet, Rev. 8 130 Freescale Semiconductor 76 54 3 2 10 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 00 00 0 0 00 Figure 9-10. Configuration Register (ADCCFG) Table 9-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required. 0 High speed configuration 1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed. 6:5 ADIV Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK. Table 9-6 shows the available clock configurations. 4 ADLSMP Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time 3:2 MODE Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See Table 9-7. 1:0 ADICLK Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See Table 9-8. Table 9-6. Clock Divide Select ADIV Divide Ratio Clock Rate 00 1 Input clock 01 2 Input clock 2 10 4 Input clock 4 11 8 Input clock 8 Table 9-7. Conversion Modes MODE Mode Description 00 8-bit conversion (N=8) 01 Reserved 10 10-bit conversion (N=10) 11 Reserved |
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