HCS08 datasheet(182/316 Pages) NXP

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Modulo Timer (S08MTIMV1)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

182

Freescale Semiconductor

12.1.4

Block Diagram

The block diagram for the modulo timer module is shown Figure 12-2.

Figure 12-2. Modulo Timer (MTIM) Block Diagram

12.2

External Signal Description

The MTIM includes one external signal, TCLK, used to input an external clock when selected as the

MTIM clock source. The signal properties of TCLK are shown in Table 12-1.

The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter

must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.

The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for

the pin location and priority of this function.

Table 12-1. Signal Properties

Signal

Function

I/O

TCLK

External clock source input into MTIM

BUSCLK

TCLK

SYNC

CLOCK

SOURCE

SELECT

PRESCALE

AND SELECT

DIVIDE BY

8-BIT COUNTER

(MTIMCNT)

8-BIT MODULO

(MTIMMOD)

8-BIT COMPARATOR

TRST

TSTP

CLKS

XCLK

TOIE

MTIM

INTERRUPT

REQUEST

TOF

REG

set_tof_pulse

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