HCS08 datasheet(246/290 Pages) MOTOROLA

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MC9S08GB/GT

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MOTOROLA

The SYNC command is unlike other BDC commands because the host does not necessarily know the

correct communications speed to use for BDC communications until after it has analyzed the response to

the SYNC command.

To issue a SYNC command, the host:

•

Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest

clock is normally the reference oscillator/64 or the self-clocked rate/64.)

•

Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically

one cycle of the fastest clock in the system.)

•

Removes all drive to the BKGD pin so it reverts to high impedance

•

Monitors the BKGD pin for the sync response pulse

The target, upon detecting the SYNC request from the host (which is a much longer low time than would

ever occur during normal BDC communications):

•

Waits for BKGD to return to a logic high

•

Delays 16 cycles to allow the host to stop driving the high speedup pulse

•

Drives BKGD low for 128 BDC clock cycles

•

Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD

•

Removes all drive to the BKGD pin so it reverts to high impedance

The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for

subsequent BDC communications. Typically, the host can determine the correct communication speed

within a few percent of the actual target speed and the communication protocol can easily tolerate speed

errors of several percent.

15.3.4 BDC Hardware Breakpoint

The BDC includes one relatively simple hardware breakpoint which compares the CPU address bus to a

16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged

breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction

boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction

opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather

than executing that instruction if and when it reaches the end of the instruction queue. This implies that

tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can

be set at any address.

The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to

enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the

breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC

breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select

forced (FTS = 1) or tagged (FTS = 0) type breakpoints.

The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are

more flexible than the simple breakpoint in the BDC module.

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