HCS08 datasheet(104/290 Pages) MOTOROLA

104 / 290 page

Internal Clock Generator (ICG) Module

MC9S08GB/GT

104

MOTOROLA

The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits

cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved).

OSCSTEN — Enable Oscillator in Off Mode

The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters

off mode.

1 = Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.

0 = Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and

REFST = 1.

6.5.2 ICG Control Register 2 (ICGC2)

Figure 6-13 ICG Control Register 2 (ICGC2)

LOLRE — Loss of Lock Reset Enable

The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication.

The LOLRE bit only has an effect when LOLS is set.

1 = Generate a reset request on loss of lock.

0 = Generate an interrupt request on loss of lock.

MFD — Multiplication Factor

The MFD bits control the programmable multiplication factor in the FLL loop. The value specified by

the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to the

MFD bits will not take effect if a previous write is not complete.

Table 6-7 CLKS Clock Select

CLKS[1:0]

Clock Mode

Self-clocked

FLL engaged, internal reference

FLL bypassed, external reference

FLL engaged, external reference

Bit 7

654321

Bit 0

Read:

LOLRE

MFD

LOCRE

RFD

Write:

Reset:

00000000

HCS08 bảng dữ liệu(PDF) 104 Page - Motorola, Inc