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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CY8C52LP bảng dữ liệu(PDF) 103 Page - Cypress Semiconductor |
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CY8C52LP bảng dữ liệu(HTML) 103 Page - Cypress Semiconductor |
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103 / 114 page  PSoC® 5LP: CY8C52LP Family Datasheet Document Number: 001-84933 Rev. *L Page 103 of 114 11.9.3 MHz External Crystal Oscillator For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators.. 11.9.4 kHz External Crystal Oscillator 11.9.5 External Clock Reference 11.9.6 Phase-Locked Loop Table 11-64. MHzECO DC Specifications Parameter Description Conditions Min Typ Max Units ICC Operating current[81] 13.56 MHz crystal – 3.8 – mA Table 11-65. MHzECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz Table 11-66. kHzECO DC Specifications[81] Parameter Description Conditions Min Typ Max Units ICC Operating current Low power mode; CL = 6 pF – 0.25 1.0 µA DL Drive level – – 1 µW Table 11-67. kHzECO AC Specifications[81] Parameter Description Conditions Min Typ Max Units F Frequency – 32.768 – kHz TON Startup time High power mode – 1 – s Table 11-68. External Clock Reference AC Specifications[81] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at VDDIO/2 30 50 70 % Input edge rate VIL to VIH 0.5 – – V/ns Table 11-69. PLL DC Specifications Parameter Description Conditions Min Typ Max Units IDD PLL operating current In = 3 MHz, Out = 80 MHz – 650 – µA In = 3 MHz, Out = 24 MHz – 200 – µA In = 3 MHz, Out = 67 MHz – 400 – µA Table 11-70. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency[82] 1– 48 MHz PLL intermediate frequency[83] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency[82] 24 – 80 MHz Lock time at startup – – 250 µs Jperiod-rms Jitter (rms)[81] –– 250 ps Notes 81. Based on device characterization (Not production tested). 82. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 83. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. |
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