CY8C52LP datasheet(54/114 Pages) CYPRESS

54 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 54 of 114



Adjustable LCD refresh rate from 10 Hz to 150 Hz



Ability to invert LCD display for negative image



Three LCD driver drive modes, allowing power optimization

Figure 8-5. LCD System

8.4.1 LCD Segment Pin Driver

Each GPIO pin contains an LCD driver circuit. The LCD driver

buffers the appropriate output of the LCD DAC to directly drive

the glass of the LCD. A register setting determines whether the

pin is a common or segment. The pin’s LCD driver then selects

one of the six bias voltages to drive the I/O pin, as appropriate

for the display data.

8.4.2 Display Data Flow

The LCD segment driver system reads display data and

generates the proper output voltages to the LCD glass to

produce the desired image. Display data resides in a memory

buffer in the system SRAM. Each time you need to change the

common and segment driver voltages, the next set of pixel data

moves from the memory buffer into the Port Data Registers via

DMA.

8.4.3 UDB and LCD Segment Control

A UDB is configured to generate the global LCD control signals

and clocking. This set of signals is routed to each LCD pin driver

through a set of dedicated LCD global routing channels. In

addition to generating the global LCD control signals, the UDB

also produces a DMA request to initiate the transfer of the next

frame of LCD data.

8.4.4 LCD DAC

The LCD DAC generates the contrast control and bias voltage

for the LCD system. The LCD DAC produces up to five LCD drive

voltages plus ground, based on the selected bias ratio. The bias

voltages are driven out to GPIO pins on a dedicated LCD bias

bus, as required.

8.5 CapSense

The CapSense system provides a versatile and efficient means

for measuring capacitance in applications such as touch sense

buttons, sliders, proximity detection, etc. The CapSense system

uses a configuration of system resources, including a few

hardware functions primarily targeted for CapSense. Specific

resource usage is detailed in the CapSense component in PSoC

Creator.

A capacitive sensing method using a delta-sigma modulator

(CSD) is used. It provides capacitance sensing using a switched

capacitor technique with a delta-sigma modulator to convert the

sensing current to a digital code.

8.6 Temp Sensor

Die temperature is used to establish programming parameters

for writing flash. Die temperature is measured using a dedicated

sensor based on a forward biased transistor. The temperature

sensor has its own auxiliary ADC.

8.7 DAC

The CY8C32 parts contain a DAC. The DAC is 8-bit and can be

configured for either voltage or current output. The DAC supports

CapSense, power supply regulation, and waveform generation.

The DAC has the following features:



Adjustable voltage or current output in 255 steps



Programmable step size (range selection)



Eight bits of calibration to correct ± 25% of gain error



Source and sink option for current output



8-Msps conversion rate for current output



1-Msps conversion rate for voltage output



Monotonic in nature



Data and strobe inputs can be provided by the CPU or DMA,

or routed directly from the DSI



Dedicated low-resistance output pin for high-current mode

LCD Driver

Block

UDB

DMA

Display

RAM

LCD

DAC

Global

Clock

PHUB

CY8C52LP bảng dữ liệu(PDF) 54 Page - Cypress Semiconductor

CY8C52LP bảng dữ liệu(HTML) 54 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL