CY8C52LP datasheet(30/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 30 of 114

consumption of the boost circuit. Only minimal power is provided,

typically < 5 µA to power the PSoC device in Sleep mode. The

boost typically draws 250 µA in active mode and 25 µA in

standby mode. The boost operating modes must be used in

conjunction with chip power modes to minimize total power

consumption. Table 6-4 lists the boost power modes available in

different chip power modes.

6.2.2.1

Boost Firmware Requirements

To ensure boost inrush current is within specification at startup,

the Enable Fast IMO During Startup value must be unchecked

in the PSoC Creator IDE. The Enable Fast IMO During Startup

option is found in PSoC Creator in the design wide resources

(cydwr) file System tab. Un-checking this option configures the

device to run at 12 MHz vs 48 MHz during startup while

configuring the device. The slower clock speed results in

reduced current draw through the boost circuit.

6.2.2.2

Boost Design Process

Correct operation of the boost converter requires specific

component values determined for each designs unique

operating conditions. The CBAT capacitor, Inductor, Schottky

diode, and CBOOST capacitor components are required with the

values specified in the electrical specifications, Table 11-7 on

page 66. The only variable component value is the inductor

LBOOST which is primarily sized for correct operation of the boost

across operating conditions and secondarily for efficiency.

Additional operating region constraints exist for VOUT, VBAT, IOUT,

and TA.

The following steps must be followed to determine boost

converter operating parameters and LBOOST value.

1. Choose desired VBAT, VOUT, TA, and IOUT operating condition

ranges for the application.

2. Determine if VBAT and VOUT ranges fit the boost operating

range based on the T

A range over VBAT and VOUT chart,

Figure 11-8 on page 66. If the operating ranges are not met,

modify the operating conditions or use an external boost

regulator.

3. Determine if the desired ambient temperature (TA) range fits

the ambient temperature operating range based on the T

range over VBAT and VOUT chart, Figure 11-8 on page 66. If

the temperature range is not met, modify the operating condi-

tions and return to step 2, or use an external boost regulator.

4. Determine if the desired output current (IOUT) range fits the

output current operating range based on the I

OUT range over

VBAT and VOUT chart, Figure 11-9 on page 66. If the output

current range is not met, modify the operating conditions and

return to step 2, or use an external boost regulator.

5. Find the allowed inductor values based on the L

BOOST values

over VBAT and VOUT chart, Figure 11-10 on page 66.

6. Based on the allowed inductor values, inductor dimensions,

inductor cost, boost efficiency, and VRIPPLE choose the

optimum inductor value for the system. Boost efficiency and

VRIPPLE typical values are provided in the Efficiency vs VBAT

and V

RIPPLE vs VBAT charts, Figure 11-11 on page 67 through

Figure 11-14 on page 67. In general, if high efficiency and low

VRIPPLE are most important, then the highest allowed inductor

value should be used. If low inductor cost or small inductor

size are most important, then one of the smaller allowed

inductor values should be used. If the allowed inductor(s)

efficiency, VRIPPLE, cost or dimensions are not acceptable for

the application than an external boost regulator should be

used.

6.3 Reset

CY8C52LP has multiple internal and external reset sources

available. The reset sources are:



Power source monitoring: The analog and digital power

voltages, VDDA, VDDD, VCCA, and VCCD are monitored in

several different modes during power up, active mode, and

sleep mode (buzzing). If any of the voltages goes outside

predetermined ranges then a reset is generated. The monitors

are programmable to generate an interrupt to the processor

under certain conditions before reaching the reset thresholds.



External: The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull up to VDDIO1. VDDD, VDDA, and VDDIO1 must

all have voltage applied before the part comes out of reset.



Watchdog timer: A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.



Software: The device can be reset under program control.

Table 6-4. Chip and Boost Power Modes Compatibility

Chip Power Modes

Boost Power Modes

Chip-active or alternate

active mode

Boost must be operated in its active

mode.

Chip-sleep mode

Boost can be operated in either active

or standby mode. In boost standby

mode, the chip must wake up periodi-

cally for boost active-mode refresh.

Chip-hibernate mode

Boost can be operated in its active

mode. However, it is recommended not

to use the boost in chip hibernate mode

due to the higher current consumption

in boost active mode.

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