CY8C52LP datasheet(55/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 55 of 114

Figure 8-6. DAC Block Diagram

8.7.1 Current DAC

The IDAC can be configured for the ranges 0 to 31.875 µA, 0 to

255 µA, and 0 to 2.04 mA. The IDAC can be configured to source

or sink current.

8.7.2 Voltage DAC

For the VDAC, the current DAC output is routed through

resistors. The two ranges available for the VDAC are 0 to 1.02 V

and 0 to 4.08 V. In voltage mode any load connected to the

output of a DAC should be purely capacitive (the output of the

VDAC is not buffered).

9. Programming, Debug Interfaces,

Resources

The Cortex-M3 has internal debugging components, tightly

integrated with the CPU, providing the following features:



JTAG or SWD access



FPB block for implementing breakpoints and code patches



DWT block for implementing watchpoints, trigger resources,

and system profiling



ETM for instruction trace



ITM for support of printf-style debugging

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

Four interfaces are available: JTAG, SWD, SWV, and

TRACEPORT. JTAG and SWD support all programming and

debug features of the device. JTAG also supports standard JTAG

scan chains for board level test and chaining multiple JTAG

devices to a single JTAG connection. The SWV and

TRACEPORT provide trace output from the DWT, ETM, and

ITM. TRACEPORT is faster but uses more pins. SWV is slower

but uses only one pin.

For more information on PSoC 5 programming, refer to the

PSoC 5 Device Programming Specification.

Cortex-M3 debug and trace functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV

interfaces are fully compatible with industry standard third party

tools.

All Cortex-M3 debug and trace modules are disabled by default

and can only be enabled in firmware. If not enabled, the only way

to reenable them is to erase the entire device, clear flash

protection, and reprogram the device with new firmware that

enables them. Disabling debug and trace features, robust flash

protection, and hiding custom analog and digital functionality

inside the PSoC device provide a level of security not possible

with multichip application solutions. Additionally, all device

interfaces can be permanently disabled (Device Security) for

applications concerned about phishing attacks due to a

maliciously reprogrammed device. Permanently disabling

interfaces is not recommended in most applications because the

designer then cannot access the device later. Because all

programming, debug, and test interfaces are disabled when

Device Security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

Reference

Source

Scaler

I source Range

1x , 8x , 64x

I sink Range

1x , 8x , 64x

Vout

Iout

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