CY8C52LP datasheet(47/114 Pages) CYPRESS

47 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 47 of 114

7.7 I2C

PSoC includes a single fixed-function I2C peripheral. Additional

I2C interfaces can be instantiated using Universal Digital Blocks

(UDBs) in PSoC Creator, as required.

The I2C peripheral provides a synchronous two-wire interface

designed to interface the PSoC device with a two-wire I2C serial

communication bus. It is compatible[12] with I2C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204). The I2C bus

I/O may be implemented with GPIO or SIO in open-drain modes.

To eliminate the need for excessive CPU intervention and

overhead, I2C specific support is provided for status detection

and generation of framing bits. I2C operates as a slave, a master,

or multimaster (Slave and Master)[12]. In slave mode, the unit

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

externally generated Start conditions. I2C interfaces through the

DSI routing and allows direct connections to any GPIO or SIO

pins.

I2C provides hardware address detect of a 7-bit address without

CPU intervention. Additionally the device can wake from low

power modes on a 7-bit hardware address match. If wakeup

functionality is required, I2C pin connections are limited to one of

two specific pairs of SIO pins. See descriptions of SCL and SDA

pins in Pin Descriptions on page 11.

I2C features include:



Slave and master, transmitter, and receiver operation



Byte processing for low CPU overhead



Interrupt or polling CPU interface



Support for bus speeds up to 1 Mbps



7 or 10-bit addressing (10-bit addressing requires firmware

support)



SMBus operation (through firmware support - SMBus

supported in hardware in UDBs)



7-bit hardware address compare



Wake from low power modes on address match



Glitch filtering (active and alternate-active modes only)

Data transfers follow the format shown in Figure 7-16. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

Figure 7-16. I2C Complete Transfer Timing

7.7.1 External Electrical Connections

As Figure 7-17 shows, the I2C bus requires external pull-up

resistors (RP). These resistors are primarily determined by the

supply voltage, bus speed, and bus capacitance. For detailed

information on how to calculate the optimum pull-up resistor

value for your design, we recommend using the UM10204

I2C-bus specification and user manual Rev 6, or newer, available

from the NXP website at www.nxp.com.

Figure 7-17. Connection of Devices to the I2C Bus

Notes

11. The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital

glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical

Specifications in “Inputs and Outputs” section on page 68 for details.

12. Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based

I2C component should be used instead.

SDA

SCL

1 - 7

START

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

Condition

CY8C52LP bảng dữ liệu(PDF) 47 Page - Cypress Semiconductor

CY8C52LP bảng dữ liệu(HTML) 47 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL