CY8C52LP datasheet(63/114 Pages) CYPRESS

63 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 63 of 114

Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V,

Temperature = 25 °C

Figure 11-2. IDD vs Frequency at 25 °C

Figure 11-3. Active Mode Current vs Temperature and FCPU,

VDD = 3.3 V

Figure 11-4. Active Mode Current vs VDD and Temperature,

FCPU = 24 MHz

20406080

CPU Frequency, MHz

0.4

0.5

0.6

0.7

0.1

0.2

0.3

204060

Bus Clock, MHz

80 MHz

24 MHz

6MH

-40

-20

20406080

100

Temperature, °C

6 MHz

105 °C

25 °C

1.522.533.544.555.5

DD, V

-40 °C

Note

25. Based on device characterization (not production tested).

Table 11-3. AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

FCPU

CPU frequency

1.71 V

 VDDD  5.5 V

–

80.01

MHz

FBUSCLK

Bus frequency

1.71 V

 VDDD  5.5 V

–

80.01

MHz

SVDD

VDD ramp rate

–

0.066

V/µs

TIO_INIT[25]

Time from VDDD/VDDA/VCCD/VCCA IPOR to

I/O ports set to their reset states

–

µs

TSTARTUP[25]

Time from VDDD/VDDA/VCCD/VCCA  PRES to

CPU executing code at reset vector

VCCA/VDDA = regulated from

VDDA/VDDD, no PLL used, fast

IMO boot mode (48 MHz typ.)

–

µs

VCCA/VCCD = regulated from

VDDA/VDDD, no PLL used, IMO

boot mode (12 MHz typ.)

–

µs

TSLEEP[25]

Wakeup from sleep mode –

Application of non-LVD interrupt to beginning

of execution of next CPU instruction

–

µs

THIBERNATE[25] Wakeup form hibernate mode – Application of

external interrupt to beginning of execution of

next CPU instruction

––

150

µs

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