CY8C52LP datasheet(27/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 27 of 114

6.2.1 Power Modes

PSoC 5LP devices have four different power modes, as shown

in Table 6-2 and Table 6-3. The power modes allow a design to

easily provide required functionality and processing power while

simultaneously minimizing power consumption and maximizing

battery life in low power and portable devices.

PSoC 5LP power modes, in order of decreasing power

consumption are:



Active



Alternate Active



Sleep



Hibernate

Active is the main processing mode. Its functionality is

configurable. Each power controllable subsystem is enabled or

disabled by using separate power configuration template

registers. In alternate active mode, fewer subsystems are

enabled, reducing power. In sleep mode most resources are

disabled regardless of the template settings. Sleep mode is

optimized to provide timed sleep intervals and Real Time Clock

functionality. The lowest power mode is hibernate, which retains

from I/O pins. Figure 6-5 illustrates the allowable transitions

between power modes. Sleep and hibernate modes should not

be entered until all VDDIO supplies are at valid voltage levels.

Table 6-2. Power Modes

Power Modes

Description

Entry Condition Wakeup Source

Active Clocks

Regulator

Active

Primary mode of operation, all

peripherals available (program-

mable)

Wakeup, reset,

manual register

entry

Any interrupt

Any (program-

mable)

All regulators available.

Digital and analog

regulators can be disabled

if external regulation used.

Alternate

Active

Similar to Active mode, and is

typically configured to have

fewer peripherals active to

reduce power. One possible

configuration is to use the UDBs

for processing, with the CPU

turned off

Manual register

entry

Any interrupt

Any (program-

mable)

All regulators available.

Digital and analog

regulators can be disabled

if external regulation used.

Sleep

All subsystems automatically

disabled

Manual register

entry

Comparator,

PICU, I2C, RTC,

CTW, LVD

ILO/kHzECO

Both digital and analog

regulators buzzed.

Digital and analog

regulators can be disabled

if external regulation used.

Hibernate

All subsystems automatically

disabled

Lowest power consuming mode

with all peripherals and internal

regulators disabled, except

hibernate regulator is enabled

Configuration and memory

contents retained

Manual register

entry

PICU

Only hibernate regulator

active.

Table 6-3. Power Modes Wakeup Time and Power Consumption

Sleep

Modes

Wakeup

Time

Current

(Typ)

Code

Execution

Digital

Resources

Analog

Resources

Clock Sources

Available

Wakeup Sources

Reset

Sources

Active

–

3.1 mA[7]

Yes

All

–

All

Alternate

Active

–

User

defined

All

–

All

Sleep

<25 µs

2 µA

I2C

Comparator

ILO/kHzECO

Comparator,

PICU, I2C, RTC,

CTW, LVD

XRES, LVD,

WDR

Hibernate

<200 µs

300 nA

None

PICU

XRES

Note

7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 61

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