CY8C52LP datasheet(5/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 5 of 114

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C52LP family these blocks can include four 16-bit timers,

counters, and PWM blocks; I2C slave, master, and multimaster;

Full-Speed USB.

For more details on the peripherals see the “Example

Peripherals” section on page 39 of this datasheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 39 of this datasheet.

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 1% error over

temperature and voltage. The configurable analog subsystem

includes:



Analog muxes



Comparators



Voltage references



ADC



DAC

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals.

The CY8C52LP family offers a SAR ADC. Featuring 12-bit

conversions at up to 1 M samples per second, it also offers low

nonlinearity and offset errors and SNR better than 70 dB. It is

well suited for a variety of higher speed analog applications.

A high-speed voltage or current DAC supports 8-bit output

signals at an update rate of 8 Msps in IDAC and 1 Msps in VDAC.

It can be routed out of any GPIO pin. You can create higher

resolution voltage PWM DAC outputs using the UDB array. This

can be used to create a pulse width modulated (PWM) DAC of

up to 10 bits, at up to 48 kHz. The digital DACs in each UDB

support PWM, PRS, or delta-sigma algorithms with

programmable widths.

In addition to the ADC and DAC, the analog subsystem provides

multiple comparators. See the “Analog Subsystem” section on

page 49 of this datasheet for more details.

PSoC’s CPU subsystem is built around a 32-bit three-stage

pipelined ARM Cortex-M3 processor running at up to 80 MHz.

The Cortex-M3 includes a tightly integrated nested vectored

interrupt controller (NVIC) and various debug and trace modules.

The overall CPU subsystem includes a DMA controller, flash

cache, and RAM. The NVIC provides low latency, nested

interrupts, and tail-chaining of interrupts and other features to

increase the efficiency of interrupt handling. The DMA controller

enables peripherals to exchange data without CPU involvement.

This allows the CPU to run slower (saving power) or use those

CPU cycles to improve the performance of firmware algorithms.

The flash cache also reduces system power consumption by

allowing less frequent flash access.

PSoC’s nonvolatile subsystem consists of flash, byte-writeable

EEPROM, and nonvolatile configuration options. It provides up

to 256 KB of on-chip flash. The CPU can reprogram individual

blocks of flash, enabling boot loaders. You can enable an ECC

for high-reliability applications. A powerful and flexible protection

model secures your sensitive information, allowing selective

memory block locking for read and write protection. Two KB of

byte-writable EEPROM is available on-chip to store application

data. Additionally, selected configuration options such as boot

speed and pin drive mode are stored in nonvolatile memory. This

allows settings to activate immediately after power-on reset

(POR).

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the VDDIO pins. Every GPIO

has analog I/O, LCD drive, CapSense, flexible interrupt

generation, slew rate control, and digital I/O capability. The SIOs

on PSoC allow VOH to be set independently of VDDIO when used

as outputs. When SIOs are in input mode they are high

impedance. This is true even when the device is not powered or

when the pin voltage goes above the supply voltage. This makes

the SIO ideally suited for use on an I2C bus where the PSoC may

not be powered when other devices on the bus are. The SIO pins

also have high current sink capability for applications such as

LED drives. The programmable input threshold feature of the

SIO can be used to make the SIO function as a general purpose

analog comparator. For devices with Full-Speed USB, the USB

physical interface is also provided (USBIO). When not using

USB these pins may also be used for limited digital functionality

and device programming. All the features of the PSoC I/Os are

covered in detail in the “I/O System and Routing” section on

page 32 of this datasheet.

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The internal main oscillator (IMO) is the master clock base for

the system and has 2% accuracy at 3 MHz. The IMO can be

configured to run from 3 MHz up to 74 MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

system clock frequencies up to 80 MHz from the IMO, external

crystal, or external reference clock. It also contains a separate,

very low-power internal low-speed oscillator (ILO) for the sleep

and watchdog timers. A 32.768-kHz external watch crystal is

also supported for use in RTC applications. The clocks, together

with programmable clock dividers, provide the flexibility to

integrate most timing requirements.

The CY8C52LP family supports a wide supply operating range

from 1.71 to 5.5 V. This allows operation from regulated supplies

such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or

directly from a wide range of battery types. In addition, it provides

an integrated high-efficiency synchronous boost converter that

can power the device from supply voltages as low as 0.5 V. This

enables the device to be powered directly from a single battery.

In addition, you can use the boost converter to generate other

voltages required by the device, such as a 3.3 V supply for LCD

glass drive. The boost’s output is available on the VBOOST pin,

allowing other devices in the application to be powered from the

PSoC.

PSoC supports a wide range of low-power modes. These include

a 300 nA hibernate mode with RAM retention and a 2-µA sleep

mode with RTC. In the second mode the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low-power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 3.1 mA when the CPU is running at

6MHz.

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