CY8C52LP datasheet(25/114 Pages) CYPRESS

25 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 25 of 114

The central timewheel can be programmed to wake the system

periodically and optionally issue an interrupt. This enables

flexible, periodic wakeups from low power modes or coarse

timing applications. Systems that require accurate timing should

use the RTC capability instead of the central timewheel.

The 100-kHz clock (CLK100K) can be used as a low power

system clock to run the CPU. It can also generate time intervals

using the fast timewheel.

The fast timewheel is a 5-bit counter, clocked by the 100-kHz

clock. It features programmable settings and automatically

resets when the terminal count is reached. An optional interrupt

can be generated each time the terminal count is reached. This

enables flexible, periodic interrupts of the CPU at a higher rate

than is allowed using the central timewheel.

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

6.1.2 External Oscillators

Figure 6-1 shows that there are two external oscillators. They

can be routed directly or divided. The direct routes may not have

a 50% duty cycle. Divided clocks have a 50% duty cycle.

6.1.2.1

MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see Internal Low

Speed Oscillator). The GPIO pins connecting to the external

crystal and capacitors are fixed. MHzECO accuracy depends on

the crystal chosen.

Figure 6-2. MHzECO Block Diagram

6.1.2.2

32.768 kHz ECO

The 32.768-kHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768-kHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1-second interrupt to

implement the RTC functionality in firmware.

The oscillator works in two distinct power modes. This allows you

to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

Figure 6-3. 32kHzECO Block Diagram

It is recommended that the external 32.768-kHz watch crystal

have a load capacitance (CL) of 6 pF or 12.5 pF. Check the

crystal manufacturer's datasheet. The two external capacitors,

CL1 and CL2, are typically of the same value, and their total

capacitance, CL1CL2 / (CL1 + CL2), including pin and trace

capacitance, should equal the crystal CL value. For more infor-

mation, refer to application note AN54439: PSoC 3 and PSoC 5

External Oscillators. See also pin capacitance specifications in

the “GPIO” section on page 68.

6.1.2.3

Digital System Interconnect

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and UDBs.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

6.1.3 Clock Distribution

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.



The system clock is used to select and supply the fastest clock

in the system for general system clock requirements and clock

synchronization of the PSoC device.



Bus Clock 16-bit divider uses the system clock to generate the

system’s bus clock used for data transfers and the CPU. The

CPU clock is directly derived from the bus clock.



Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, the Universal Digital Blocks (UDBs) and fixed function

timer/counter/PWMs can also generate clocks.

(Pin P15[0])

4 - 25 MHz

Crystal Osc

XCLK_MHZ

4 – 25 MHz

crystal

Capacitors

External

Components

(Pin P15[1])

(Pin P15[2])

32 kHz

Crystal Osc

XCLK32K

32 kHz

crystal

Capacitors

External

Components

(Pin P15[3])

CY8C52LP bảng dữ liệu(PDF) 25 Page - Cypress Semiconductor

CY8C52LP bảng dữ liệu(HTML) 25 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL