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CY8C52LP bảng dữ liệu(PDF) 35 Page - Cypress Semiconductor |
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CY8C52LP bảng dữ liệu(HTML) 35 Page - Cypress Semiconductor |
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35 / 114 page ![]() PSoC® 5LP: CY8C52LP Family Datasheet Document Number: 001-84933 Rev. *L Page 35 of 114 6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-12 depicts a simplified pin view based on each of the eight drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-12. Drive Mode Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High impedance analog 0 0 0 High-Z High-Z 1 High Impedance digital 0 0 1 High-Z High-Z 2 Resistive pull-up[9] 0 1 0 Res High (5K) Strong Low 3 Resistive pull-down[9] 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High-Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High-Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull-up and pull-down[9] 1 1 1 Res High (5K) Res Low (5K) Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin 0. High Impedance Analog 1. High Impedance Digital 2. Resistive Pull-Up 3. Resistive Pull-Down 4. Open Drain, Drives Low 5. Open Drain, Drives High 6. Strong Drive 7. Resistive Pull-Up and Pull-Down VDD VDD VDD VDD VDD An An An An An An An An The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register (when HW connection is disabled). The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected. The ‘An’ connection connects to the Analog System. Note 9. Resistive pull up and pull down are not available with SIO in regulated output mode. |
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