CY8C52LP datasheet(48/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 48 of 114

For most designs, the default values in Table 7-2 will provide

excellent performance without any calculations. The default

values were chosen to use standard resistor values between the

minimum and maximum limits. The values in Table 7-2 work for

designs with 1.8 V to 5.0V VDD, less than 200-pF bus capaci-

tance (CB), up to 25 µA of total input leakage (IIL), up to 0.4 V

output voltage level (VOL), and a max VIH of 0.7 * VDD. Standard

Mode and Fast Mode can use either GPIO or SIO PSoC pins.

Fast Mode Plus requires use of SIO pins to meet the VOL spec

at 20 mA. Calculation of custom pull-up resistor values is

required; if your design does not meet the default assumptions,

you use series resistors (RS) to limit injected noise, or you need

to maximize the resistor value for low power consumption.

Calculation of the ideal pull-up resistor value involves finding a

value between the limits set by three equations detailed in the

NXP I2C specification. These equations are:

Equation 1:

Equation 2:

Equation 3:

Equation parameters:

VDD = Nominal supply voltage for I2C bus

VOL = Maximum output low voltage of bus devices.

IOL= Low-level output current from I2C specification

TR = Rise Time of bus from I2C specification

CB = Capacitance of each bus line including pins and PCB traces

VIH = Minimum high-level input voltage of all bus devices

VNH = Minimum high-level input noise margin from I2C specifi-

cation

IIH = Total input leakage current of all devices on the bus

The supply voltage (VDD) limits the minimum pull-up resistor

value due to bus devices maximum low output voltage (VOL)

specifications. Lower pull-up resistance increases current

though the pins and can, therefore, exceed the spec conditions

of VOH. Equation 1 is derived using Ohm's law to determine the

minimum resistance that will still meet the VOL specification at

3 mA for standard and fast modes, and 20 mA for fast mode plus

at the given VDD.

Equation 2 determines the maximum pull-up resistance due to

bus capacitance. Total bus capacitance is comprised of all pin,

wire, and trace capacitance on the bus. The higher the bus

capacitance, the lower the pull-up resistance required to meet

the specified bus speeds rise time due to RC delays. Choosing

a pull-up resistance higher than allowed can result in failing

timing requirements resulting in communication errors. Most

designs with five or less I2C devices and up to 20 centimeters of

bus trace length have less than 100 pF of bus capacitance.

A secondary effect that limits the maximum pull-up resistor value

is total bus leakage calculated in Equation 3. The primary source

of leakage is I/O pins connected to the bus. If leakage is too high,

the pull-ups will have difficulty maintaining an acceptable VIH

level causing communication errors. Most designs with five or

less I2C devices on the bus have less than 10 µA of total leakage

current.

Table 7-2. Recommended default Pull-up Resistor Values

Units

Standard Mode – 100 kbps

4.7 k, 5%

Ω

Fast Mode – 400 kbps

1.74 k, 1%

Ω

Fast Mode Plus – 1 Mbps

620, 5%

Ω

PMIN

DD max

 V

–

max



 I

OL min





PMAX

R max

 0.8473 C

B max







PMAX

DD min

 V

IH min



–

NH min

 I

IH max





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