CY8C52LP datasheet(37/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 37 of 114

6.4.5 Pin Interrupts

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own port

interrupt control unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to “1” and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

vector in the interrupt controller and the pin status register

providing easy determination of the interrupt source down to the

pin level.

Port pin interrupts remain active in all sleep modes allowing the

PSoC device to wake from an externally generated interrupt.

While level sensitive interrupts are not directly supported; UDBs

provide this functionality to the system when needed.

6.4.6 Input Buffer Mode

GPIO and SIO input buffers can be configured at the port level

for the default CMOS input thresholds or the optional LVTTL

input thresholds. All input buffers incorporate Schmitt triggers for

input hysteresis. Additionally, individual pin input buffers can be

disabled in any drive mode.

6.4.7 I/O Power Supplies

Up to four I/O pin power supplies are provided depending on the

device and package. Each I/O supply must be less than or equal

to the voltage on the chip’s analog (VDDA) pin. This feature

allows you to provide different I/O voltage levels for different pins

on the device. Refer to the specific device package pinout to

determine VDDIO capability for a given port and pin.

The SIO port pins support an additional regulated high output

capability, as described in Adjustable Output Level.

6.4.8 Analog Connections

These connections apply only to GPIO pins. All GPIO pins may

be used as analog inputs or outputs. The analog voltage present

on the pin must not exceed the VDDIO supply voltage to which

the GPIO belongs. Each GPIO may connect to one of the analog

global busses or to one of the analog mux buses to connect any

pin to any internal analog resource such as ADC or comparators.

In addition, one select pin provides direct connection to the high

current DAC.

6.4.9 CapSense

This section applies only to GPIO pins. All GPIO pins may be

used to create CapSense buttons and sliders[10]. See the

“CapSense” section on page 54 for more information.

6.4.10 LCD Segment Drive

This section applies only to GPIO pins. All GPIO pins may be

used to generate Segment and Common drive signals for direct

glass drive of LCD glass. See the “LCD Direct Drive” section on

page 53 for details.

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support the

ability to provide a regulated high output level for interface to

external signals that are lower in voltage than the SIO’s

respective VDDIO. SIO pins are individually configurable to

output either the standard VDDIO level or the regulated output,

which is based on an internally generated reference. Typically

the voltage DAC (VDAC) is used to generate the reference (see

Figure 6-13). The DAC on page 54 has more details on VDAC

use and reference routing to the SIO pins. Resistive pull up and

pull down drive modes are not available with SIO in regulated

output mode.

6.4.12 Adjustable Input Level

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

interface to external signals that differ in voltage from VDDIO.

The reference sets the pins voltage threshold for a high logic

level (see Figure 6-13). Available input thresholds are:



0.5

VDDIO



0.4

VDDIO



0.5

VREF



VREF

Typically the voltage DAC (VDAC) generates the VREF

reference. The DAC on page 54 has more details on VDAC use

and reference routing to the SIO pins.

Note

10. GPIOs with opamp outputs are not recommended for use with CapSense.

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