CY8C52LP datasheet(57/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 57 of 114

9.2 SWD Interface

The SWD interface is the preferred alternative to the JTAG

interface. It requires only two pins instead of the four or five

needed by JTAG. SWD provides all of the programming and

debugging features of JTAG at the same speed. SWD does not

provide access to scan chains or device chaining. The SWD

clock frequency can be up to 1/3 of the CPU clock frequency.

SWD uses two pins, either two of the JTAG pins (TMS and TCK)

or the USBIO D+ and D- pins. The USBIO pins are useful for in

system programming of USB solutions that would otherwise

require a separate programming connector. One pin is used for

the data clock and the other is used for data input and output.

SWD can be enabled on only one of the pin pairs at a time. This

only happens if, within 8 μs (key window) after reset, that pin pair

(JTAG or USB) receives a predetermined acquire sequence of

1s and 0s. If the NVL latches are set for SWD (see Section 5.5),

this sequence need not be applied to the JTAG pin pair. The

acquire sequence must always be applied to the USB pin pair.

SWD is used for debugging or for programming the flash

memory.

The SWD interface can be enabled from the JTAG interface or

disabled, allowing its pins to be used as GPIO. Unlike JTAG, the

SWD interface can always be reacquired on any device during

the key window. It can then be used to reenable the JTAG

interface, if desired. When using SWD or JTAG pins as standard

GPIO, make sure that the GPIO functionality and PCB circuits do

not interfere with SWD or JTAG use.

Figure 9-2. SWD Interface Connections between PSoC 5LP and Programmer

VSSD, VSSA

VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3

1, 2, 3

SWDCK (P1[1] or P15[7])

SWDIO (P1[0] or P15[6])

XRES

GND

SWDCK

SWDIO

XRES

Host Programmer

PSoC 5

VDD

1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in

programming should be the same. The XRES pin is powered by VDDIO1. The USB SWD

pins are powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1

of PSoC 5 should be at the same voltage level as Host VDD. Rest of PSoC 5 voltage domains

( VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD

pins are powered by VDDIO1. So VDDIO1 of PSoC 5 should be at same voltage level as host VDD for

Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not

be at the same voltage level as host Programmer.

2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.

3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require

external interface circuitry to toggle power which will depend on the programming setup. The power

supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or

equal to all other supplies.

VDD

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