CY8C52LP datasheet(6/114 Pages) CYPRESS

6 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 6 of 114

The details of the PSoC power modes are covered in the “Power

System” section on page 26 of this datasheet.

PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for

programming, debug, and test. Using these standard interfaces

you can debug or program the PSoC with a variety of hardware

solutions from Cypress or third party vendors. The Cortex-M3

debug and trace modules include FPB, DWT, ETM, and ITM.

These modules have many features to help solve difficult debug

and trace problems. Details of the programming, test, and

debugging interfaces are discussed in the “Programming, Debug

Interfaces, Resources” section on page 55 of this datasheet.

2. Pinouts

Each VDDIO pin powers a specific set of I/O pins. (The USBIOs

are powered from VDDD.) Using the VDDIO pins, a single PSoC

can support multiple voltage levels, reducing the need for

off-chip level shifters. The black lines drawn on the pinout

diagrams in Figure 2-3 and Figure 2-4, as well as Table 2-1,

show the pins that are powered by each VDDIO.

Each VDDIO may source up to 100 mA total to its associated I/O

pins, as shown in Figure 2-1.

Figure 2-1. VDDIO Current Limit

Conversely, for the 100-pin and 68-pin devices, the set of I/O

pins associated with any VDDIO may sink up to 100 mA total, as

shown in Figure 2-2.

Figure 2-2. I/O Pins Current Limit

PSoC

VDDIO X

IDDIO X = 100 mA

I/O Pins

PSoC

VDDIO X

Ipins = 100 mA

I/O Pins

VSSD

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