CY8C52LP datasheet(56/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 56 of 114

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five

pins (the nTRST pin is optional). The JTAG clock frequency can

be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and

16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit

transfers, whichever is least. By default, the JTAG pins are

enabled on new devices but the JTAG interface can be disabled,

allowing these pins to be used as General Purpose I/O (GPIO)

instead. The JTAG interface is used for programming the flash

memory, debugging, I/O scan chains, and JTAG device chaining.

Figure 9-1. JTAG Interface Connections between PSoC 5LP and Programmer

TCK (P1[1]

TMS (P1[0])

GND

TCK

TMS

XRES

Host Programmer

PSoC 5

TDO

TDI (P1[4])

TDI

TDO (P1[3])

nTRST

nTRST (P1[5]) 6

1 The voltage levels of Host Programmer and the PSoC 5 voltage domains involved in Programming should be same.

The Port 1 JTAG pins and XRES pin are powered by VDDIO1. So, VDDIO1 of PSoC 5 should be at same

voltage level as host VDD. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same

voltage level as host Programmer.

2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.

3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4 For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by

using the TMS,TCK,TDI, TDO pins of PSoC 5, and writing to a specific register. But this requires that the DPS setting

in NVL is not equal to “Debug Ports Disabled”.

5 By default, PSoC 5 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is

unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD

Protocol has to be used for acquiring the PSoC 5 device initially. After switching from SWD to JTAG mode, the TMS

pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.

6 nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 5

as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.

VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3

1, 2, 3, 4

VSSD, VSSA

XRES

VDD

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